Integrated Circuit packaging has always been integral to IC performance and functionality. An IC package serves many purposes: 1) pitch conversion between the fine features of the IC die and the system level interconnection; 2) chemical, environmental and mechanical protection; 3) heat transfer; 4) power, ground and signal distribution between the die and system; 5) handling robustness; and 6) die identification among many others. Numerous critical technologies have been developed to serve these functions; technologies that continue to advance with each new requirement for cost reduction, space savings, higher speed electrical performance, finer pitch, die surface fragility, new reliability requirements, and new applications. Packaging engineers must fully understand these technologies to design and fabricate future high-performance packages with high yields at exceptional low-costs to give their company a critical competitive advantage.

IC Packaging Technology is a 2-day course that details the vital technologies required to construct IC packages in a reliable, cost effective, and quick time to market fashion. When completed, the participant will understand the wide array of technologies available; how technologies interact; what choices must be made for a high-performance product vs. a consumer device; and how such choices impact the manufacturability, functionality, and reliability of the finished product. An emphasis will be given to manufacturing; processes; and materials selection, tailoring, and development. Each fundamental package family will be discussed, including flip chip area array technologies, Wafer Level Packaging (WLP), Fan-Out Wafer Level Packaging (FO-WLP), and the latest Through Silicon Via (TSV) developments. Additionally, future directions for each package technology will be highlighted, along with challenges that must be surmounted to succeed.

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller. The question looming in everyone’s mind is “How far into the future can this continue?” Advanced CMOS/FinFET Fabrication is a 2-day course that offers detailed instruction on the processing used in a modern integrated circuit, and the processing technologies required to make them. We place special emphasis on current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.

By concentrating on the latest developments in CMOS and FinFET technology, participants will learn why FinFETs are fast becoming the technologies of choice at feature sizes below 20nm. Our instructors work hard to explain semiconductor processing without delving heavily into the complex physics and materials science that normally accompany this discipline.

Attend to hear research, challenges, and breakthroughs as you gather with colleagues in San Jose

Join other leading researchers who are solving challenges in optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications.

The MEMS & Sensors Technical Congress is designed for technical executives and engineers with a special focus on designers, product engineers, fabrication technologists, and application engineers. 

DRIVING SEMICONDUCTOR BUSINESS IN THE MIDWEST 

Join us for a groundbreaking Midwest conference and tradeshow on April 1-2, 2025, focused on Smart Manufacturing and Smart Mobility with an emphasis on the semiconductor industry! Automotive electronics and smart manufacturing are two of the key end markets on the path to $1T in semiconductor revenue. 

A significant amount of both markets is concentrated in the Midwestern United States. SEMIEXPO Heartland will bring these two key markets together and provide an opportunity for collaboration and growth.

Areas of Focus—

Engineering, Design & Development

Smart Manufacturing

Mobility and Automotive Manufacturing

Semiconductor