JIM STRAUS, Vice President of Sales, ACM Research
The rapid demand for artificial intelligence (AI) and high-bandwidth memory (HBM) devices that can handle massive data processing and are large in size (~800 mm2) is driving the industry transition to chiplets. While chiplets have been in use for decades, they’ve been employed sparingly and for very specific purposes. Now, they’re at the cutting edge of technology for desktop PCs, workstations, and servers. Chiplets are segmented processors with specific sections manufactured as separate chips. These individual chips are then mounted together into a single package using a complex connection system.
The fast adoption of chiplets will continue to drive wafer-level packaging (WLP) growth in 2025, as semiconductor companies continue to invest in various types of packages for diverse applications, including automotive, CMOS sensors, MEMS, RF filters, and more. These high-demand WLPs include die-to-die, die-to-wafer, wafer-to-wafer, and fan-out wafer-level packaging. However, the industry is experiencing capacity constraints due to the large size of these packages.
Panel-level packaging (PLP) has many advantages over WLP. PLP enables the industry to significantly increase the substrate area for building chiplets, improving yield and reducing packaging costs. The larger area allows more chips to be assembled at the same time, increasing capacity and reducing supply constraints. Fan-out panel-level packaging (FOPLP) allows for simplified integration of various die technologies (logic, memory, and RF) into a single package that is smaller and thinner.
PLP reduces compute times and power usage, supporting a more complex system for AI and high-performance computing (HPC) applications. As a result, we expect to see growing adoption of PLP in 2025. ACM Research is supporting the transition to PLP with new substrate handling systems and improved panel cleaning and deposition technologies. ACM Research is developing a panel cleaning tool that can remove flux and contamination from the center of the panel to eliminate void formation, as well as an electroplating tool that can provide uniform deposition across a 600mm square panel.
Addressing these technical challenges will be a major hurdle in 2025, helping to ease the transition to PLP, improve capacity, and support the chip demand for the AI and HPC applications of the future.
Click here to read the 2025 Executive Viewpoints in Semiconductor Digest
