DR. THOMAS UHRMANN, Director of Business Development, EV Group
To continue scaling the power density of future semiconductor components, there is no way around 3D integration. The aspect of system performance is central. Depending on the system requirements, various bonding technologies such as solder connections, thermocompression and hybrid bonding can be selected. At the same time, wafer bonding is a decisive factor for 3D integration. It can even be argued that wafer bonding is the new lithography scaling, without which there would be no possibility for future stacked processors, memories and heterogeneously integrated systems.
As we approach the new year, several new design and manufacturing techniques that rely on wafer bonding are finally moving into mainstream manufacturing. One such technique is backside power delivery networks, via bonding and extreme thinning of the CMOS wafer on a new carrier substrate. Backside power delivery relocates power to the back of the wafer and leaves only signals to be transmitted through frontside interconnects to provide wider power lines with reduced IR drop, a more uniform voltage distribution, and more design space, which allows for further scaling of the standard cell height. Due to the extremely high overlay accuracy required for the bonded wafers in backside power delivery, co-optimization of wafer bonding and lithography have become essential for this technique.
Another emerging technique where wafer bonding is essential is chiplet integration, where small modular ICs with specific functions can be mixed and matched into complete systems – offering the potential for lower cost, higher performance and greater flexibility compared to monolithic systems. To support certain applications, such as high-performance computing (HPC), chiplets are being stacked on top of each other in a 3D system-on-chip approach, necessitating wafer-to-wafer hybrid bonding with unprecedented interconnect pitch scaling below 400nm for monolithic or recon wafers with so-called quasi-monolithic wafers.
Face-to-back integration as well as layer transfer of extremely thin materials is another emerging technique that is necessary for new architectures and design innovations such as new memory technologies and architectures, and backside power delivery networks, spanning even to future transistor designs such as complementary field-effect transistors (CFETs). The use of silicon carrier wafers and inorganic release layers in combination with infrared laser technology enables laser debonding on silicon with nanometer precision while supporting process cleanliness, material compatibility and high processing temperature requirements for front-end manufacturing flows.
Wafer bonding is truly enabling semiconductor scaling roadmaps and will take center stage, not only in 2025 but for years to come.
Click here to read the 2025 Executive Viewpoints in Semiconductor Digest
