Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the certification of the Cadence® tools in TSMC reference flows for TSMC’s latest InFO and CoWoS® advanced packaging solutions, the Integrated Fan-Out with RDL interconnect (InFO-R) and Chip-on-Wafer-on-Substrate with silicon interposer (CoWoS®-S). Through the continued collaboration between Cadence and TSMC, customers designing hyperscale and networking applications can accelerate productivity via streamlined design, analysis and verification reference flows.
With a focus on system-level power, performance and area (PPA), today’s technology innovators need to create functionally dense devices with higher performance and minimal power consumption. In an effort to provide more automation when designing these advanced packages, Cadence and TSMC developed flows for planning, designing, analyzing and verifying each unique advanced packaging technology, providing a clear path to meet design PPA objectives.
The latest reference flows offer a more efficient DRC signoff/tapeout methodology through preventive and correction design automation, enabled by the Cadence Allegro® package layout technology. Additionally, customers can achieve improved layout automation of InFO-R packages through support for a new standard InFO techfile and design macros in the Allegro Package Designer Plus in conjunction with new in-design DRC validation and improved performance in advanced de-gassing enabled by the Silicon Layout Option. Finally, the Cadence Clarity™ 3D Solver has been certified for 3D-EM extraction, including new support for S-parameter model creation for CoWoS-S designs.
“The result of our collaboration combining the Cadence tools and TSMC’s advanced packaging technologies helps our mutual customers address their design challenges for higher performance and minimal power consumption,” said Suk Lee, Senior Director of the Design Infrastructure Management Division at TSMC. “We look forward to a continued partnership with Cadence to ensure that our customers can deliver their innovations to market faster than ever.”
“Since the early 1990s, Cadence has been developing tools that enable customers to achieve advanced multi-chip packaging design excellence, and by continuing our work with TSMC on advanced packaging technologies and techniques, customers can attain a higher level of automation and design accuracy when targeting TSMC state-of-the-art packaging solutions,” said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence. “Our mutual customers can start creating designs immediately using the latest Cadence and TSMC packaging technologies for today’s emerging applications.”
