Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Pegasus Verification System has achieved the latest Design Rule Manual (DRM) certification for the TSMC N16, N12 and N7 process technologies. The Cadence Pegasus Verification System has been successfully validated by TSMC to provide customers with a fast path to meet physical verification signoff goals across several application areas including AI, automotive, processor, data center and IP applications.
Customers using the Pegasus Verification System on TSMC’s N16, N12 and N7 processes can sign off chips using the TSMC-certified rule decks, which are available for all the signoff physical verification flows such as the design rule check (DRC), layout versus schematic (LVS), and dummy fill.
“We worked closely with Cadence to deliver this certified Pegasus Verification System across several advanced TSMC processes,” said Suk Lee, senior director of Design Infrastructure Management Division at TSMC. “The result of our ongoing collaboration with Cadence helps our mutual customers meet design cycle time goals and reap the power and performance benefits of our industry-leading process technologies including N16, N12 and N7.”
“The Pegasus Verification System allows customers to massively distribute physical verification jobs on heterogeneous hardware environments without memory or CPU slot limitations, providing optimal support on TSMC’s advanced-process technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Our continued collaboration with TSMC on the Pegasus Verification System certification provides customers with confidence that they can attain consistent, accurate results and meet competitive schedules.”
The Pegasus Verification System is part of the broader Cadence digital and signoff full flow, which provides better predictability and a faster path to design closure. It supports Cadence’s Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence.
