Pat Gelsinger Takes us on a Trip Down Memory Lane – and a Look Ahead: Part 1

Lithography was done on the 2” wafers of the time by contact printing with manual alignment, and the rules of thumb were no more than five wafers per mask, and die size of no more than 5mm per side.

In the meantime, projection alignment and ion implantation were introduced, adding automation, accuracy and controllability to the whole process sequence.

Of course, we also saw lots of changes in the back end, notably the introduction of CMP and tungsten contacts, enabling multi-level metals, and steppers took over lithography. Wafer size had evolved from the 2” of the early ‘70s, through 3”, 4”, and 6” to 8” (200 mm), with a few fabs running 5” in the interim.

As a general rule, for logic parts the gate length was used as the node or generation number down to ~0.35 – not universally accurate, but generally accepted. But at a quarter micron, things started to diverge, and gates shrank faster than the node number.

In 1998 IBM introduced copper metallization at the 180-nm node (gate length ~90 nm), and at 130 nm low-k dielectrics and 300-mm wafers came into use. At 90 nm Dennard scaling really did fail; the gate oxide had thinned down to ~1 nm, at which point it leaked current like a sieve, with consequent rise in leakage power. So to keep increasing performance, Intel increased carrier mobility by adding stress to the channel. They used tensile nitride for NMOS, and SiGe embedded in the source/drain to give compressive stress for PMOS.

It’s hard to see what’s going on here, so here are some TechInsights cross-sections of the 45-nm transistors [1]:

As you can see, a completely new philosophy of gate construction. A replacement metal gate (RMG) process is used, in which a dummy polysilicon gate is formed first on top of the high-k layer, then all the source/drain engineering is done (sidewall spacers through to contact etch-stop layer and dielectric fill); CMP back to expose the dummy gate, etch it out, and fill with the gate stacks.

There are extra subtleties in that the PMOS stack is built first over the whole wafer, then in the NMOS regions it is etched back to the tantalum layer, and the NMOS stack is deposited. We can also see that the embedded SiGe in the PMOS source/drains takes the (111) planes to improve stress transfer to the channel. Not visible in these images is a change from contacts through holes to contacts in trenches.

The 32-nm structure [2] is an evolution of the 45:

The next shrink was another huge architectural change, to a FinFET structure. Intel put the RMG gate stacks over a 3D fin-shaped substrate, giving gate control on three sides of the channel.

As seen in our TEM:

The tapered fins with rounded tops should be good for reliability, but the gate width is now defined by the wrap-around distance on the fin, forcing quantization of gate width, in this case to ~70 nm. The overall fin height is ~100 nm, and the fin width is 5 – 15 nm under the gate. The functional fin height is ~34 nm, giving us a gate width of ~70nm.

Part 2 available here