EUV is late but on the way for 10nm; DSA is promising

EUV lithography is late, but it is on the way and will be ready for insertion into the 10nm node, which is slated to go into production in late 2015/early 2016. Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. These were some of the conclusions from the imec International Technology Forum for the press earlier this month, where the latest results from EUV and DSA work were presented. Imec and ASML also announced an advanced patterning center that will be based at imec’s Leuven campus focused on EUV.

Luc Van den hove, president and CEO of imec, described EUV as a cost-effective lithography approach that is “absolutely needed.” He said: “We realize that EUV is late. There are challenges here. But I have to say over the last couple of months, significant and steady progress has been realized.” In terms of imaging performance, imec has been characterizing some of the latest hardware together with ASML and have showed very good resolution performance of 13nm half pitch and 22nm contact holes. “With double patterning, we have even demonstrated 9nm half pitch,” Van den hove said. “Who would have thought a couple of years ago that this would be realizable with lithography?”

Adequate source power, which directly determines throughput, is one of the challenges. “We are seeing a steady increase quarter by quarter,” Van den hove said. “We see that we get the improvements and I’m very convinced that very soon EUV will be ready to enter manufacturing.”

An Steegen, senior vice president of process technology at imec, provided some more details: “The standalone Cymer source has been demonstrated at 55Watt. The next checkpoint is the 80W by the end of 2013. That is on the assembled system, source and scanner, and [throughput] should be approximately 58 wafers/hour. The goal is by the end of 2014, about 126 wafer/hour,” she said.

Steegen said ASML’s 3300 system has already been verified. “We definitely and clearly can see the resolution benefits as well as overlay capability,” she said (the demonstrations were done in at ASML’s facilities in Veldhoven; imec has a 3000 system installed, but won’t get a 3300 until February 2014).

The ideal entry point for EUV is the 10nm node (or N10 using imec’s terminology). “If you look at the cost calculation, the best entry point for EUV is actually at N10 because you can replace triple patterning layers in immersion with a single patterning layer in EUV,” Steegen said. Since that will come relatively soon with early production occurring toward the end of 2015 and in early 2016, that means that likely the whole development phase will have already been built on immersion and multi-patterning. “Likely you will see on the most difficult levels, a swap, an introduction of EUV at the most critical levels later on in manufacturing for N10,” Steegen said. “That is still what the forecast is today. You would also see a benefit later on inserting EUV in N10.”

When you move to N7 and do multi-patterning, it’s getting even more complicated, since almost every level is going to be triple patterning. “If you replace that with EUV, will still are going to try to have single patterning on most of the levels, but there’s some complexity coming in even with EUV, that you would have to go to multi-patterning for N7 to get to those dimensions,” Steegen added.

However, she acknowledged that more work needed to be done.

She noted that defectivity in mask and the reticles was still a challenge, particularly those defects embedded in the multi-layered films. “Between those mutli-layers in the reticle, you might have embedded defects that you can’t see today with any inspection tool. You actually need an actinic inspection tool that also runs at the wavelength of the EUV tool to really see those embedded defects on the reticle. Today, the only way we find those is by printing the wafer and see the printable defects in your patterns,” she said.  

Van den hove added: “Now that the tool is really progressing tremendously and becoming ready for manufacturing, you also have to make sure that the rest of the infrastructure is ready. In our program, we are now focusing very much also on how to handle defects – defectivity on the mask is one of the big challenges.”

In an earlier interview, Veeco’s Tim Pratt, Senior Director, Marketing, said that indeed the next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. He said that the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV.

Imec is also evaluating the use of a pellicle on EUV reticles. Pellicles are used to keep particles from falling on the reticle during exposure and transport, but since EUV masks are reflective instead of transparent, it’s no clear how a pellicle would work. “For years, we have been thinking that pellicles would be impossible in EUV, and whether we can use a pellicle or not,” Van den hove said. But he said there were some options that are being evaluated at this moment. Steegen said: “We’re looking into would it make sense to avoid added defects during scanning to introduce a pellicle on these EUV reticles.”

Steegen also said they have also seen good progress with the resists needed for EUV for the 22/20nm contact hole and line space range, including improved line edge roughness (LER) and local critical dimension uniformity (LCDU). “We see quite some improvement in LER post-etch and also in LCDU post-etch where we combined the exposures on the 3300 with etch and basically try to improve our line edge roughness and local CDU,” she said. Imec has integrated litho and etch together in such a way that the resulting dimensions are improved after etch. “What you can see is that you cannot only shrink your holes after etch, but you also improve your line edge roughness and local CDU after etch,” Steegen said. “That’s pretty significant because basically you can shrink the nominal dimension of the hole by about 14% and the local variation of that CD, we can improve about 30% post etch.”

Here’s how imec summed up EUV’s readiness:  

• NXE-3300 resolution benefit and overlay capability demonstrated.

• CH and LS resist materials for NXE-3300 selected, based on CDU, LER/LCDU and defectivity; good progress in resist process down-selection towards 16nm LS (@ 0.33NA)

• 4.2nm of CH CD reduction for 26 nm HP post etch (14%); 1.4nm LCDU reduction for 26nm HP post etch (30%)

• Source power and mask defectivity remain key challenges:

• ASML/Cymer demonstrated 55W power on standalone Cymer source, outlook 80W (58wph) by YE13,

250W (126wph) by YE14.

• Introduction of actinic inspection tools by 2015 for mask blank embedded defect detection and of pellicle to reduce mask defect adders.

• Expectation that EUV will be introduced at a few critical levels in N10 nanufacturing (replace LE3) with cost reduction benefit. Potential EUV area benefit from tip-to-tip and tip-to-line and pitch scaling, with redesign.

DSA is very promising

Van den hove described direct self-assembly (DSA) as “very promising” and Steegen said work there has largely focused on reducing defectivity. In DSA, resists that contain block copolymers are deposited on top of guiding structures. The self-directed nature of the process results in very regular patterns with very high resolution.

The trick with DSA is that it requires a double exposure to take away the random patterns at the edge of the device, and the resolution needed for this “cut mask” is also very high. “We’re convinced that it’s not a replacement for EUV or any high resolution lithography technique. We are very convinced it will be used in conjunction with EUV,” Van den hove said. “It certainly keeps the pressure on EUV very high.”

Steegen described DSA as a complimentary litho technique that is having quite some momentum. The process starts with a “relaxed” guiding pattern on your wafer.  Then, depending on the polymer length in the block copolymer, the space in between the guiding structure is replicated into multiple lines and spaces. “The defectivity of these materials are going to be key to bring the defects down. Our year end target is 60 defects/cm² and this needs to go down even further next year,” she said.

Work at imec has shown that the polymers, with a hard mask on top, are robust enough to enable the etching of the patterns into silicon. “That’s fairly new data and very promising,” Steegen said. Imec is already looking at where DSA levels could be inserted into the logic N7 flow, with fins and spacers being primary targets. Steegen said the Metal1 level would be a challenge due to its irregular pattern. “That makes it not easy to be replaced with DSA, but we’re looking into techniques to do that,” she said.

Here’s how imec summed up DSA readiness:

• Good progress in material selection and integration flow optimization for line-multiplication down to 14nm, pattern transfer into bulk Si demonstrated.

• First templated DSA process available using SOG/SOC hard mask stack.

• Focus on defectivity reduction & understanding, currently at 350 defects/cm2, YE13 target 60 def/cm2

• Alignment and overlay strategy needs to be worked out

• First N7 implementation levels identified: Finfet (replace SADP EUV or SAQP 193i) and Via (replace EUV SP/DP or 193i LE3).