Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the complete, integrated Cadence® 3D-IC advanced packaging integration flow has achieved certification for the Samsung Foundry MDI™ (Multi-Die-Integration) packaging flow based on the 7nm Low Power Process (7LPP) technology. The reference flow was developed in close collaboration with Samsung Foundry to provide mutual customers with a full planning, implementation and analysis flow for 3D multi-die packages.
The use of multiple stacked chips in a single package is becoming a key trend for mobile, IoT and data center designs, which is also extending into the AI and 5G market segments due to the rapid and efficient integration of complete functions that can be implemented via the optimal process node into a system in package (SiP). The Cadence technology provides customers with analysis, implementation and physical verification capabilities within a single canvas and offers unique, early-stage system-level pathfinding and highly-complex design capabilities for 3D signoff. The Cadence flow has been optimized to enable customers to achieve all the benefits the Samsung Foundry MDI packaging technology has to offer in order to deliver new products to market with greater speed and agility.
“Mutual customers addressing various types of design sizes and complexities can benefit from the new MDI flow based on Cadence’s flexible suite of advanced 3D packaging tools, which aims to support the integration of multiple application-specific die and chiplets into a single packaged device that is optimized for their target application,” said Jung Yun Choi, vice president of Foundry Design Technology Team at Samsung Electronics. “This collaboration between Cadence and Samsung provides customers with both reduction in cost and turnaround time through the accurate, broad analysis of system-level and complex interconnects.”
A full suite of Cadence digital and signoff as well as IC package and PCB analysis tools have been optimized for the Samsung MDI technology to guarantee seamless integration for handling multiple dies including the Innovus™ Implementation System, Quantus™ Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, OrbitIO™ interconnect designer, SiP Layout, Sigrity™ XtractIM™ technology, Sigrity XcitePI™ technology, Sigrity SystemSI™ technology, and Sigrity PowerDC™ technology.
“This is an example of how, through our continued partnership with Samsung Foundry, we’re developing innovative solutions for our mutual customers,” said KT Moore, vice president, product management, Digital & Signoff Group at Cadence. “This seamless 3D integrated flow developed by Cadence and Samsung Foundry enables our customers to design multi-die offerings in a single integrated environment, enabling the delivery of complex products much faster.”
The Cadence 3D-IC packaging flow provides a fast path to design closure and supports the company’s overall Intelligent System Design™ strategy, enabling advanced-node system-on-chip (SoC) design excellence.
