Synopsys, Inc. (Nasdaq: SNPS) today announced that GLOBALFOUNDRIES® (GF®) has qualified Synopsys’ IC Validator for its 22FDX® platform. With IC Validator physical verification, customers striving to take advantage of the low-power and performance benefits of GF’s 22-nanometer FD-SOI technology can now quickly verify that their designs meet signoff requirements for manufacturability compliance and maximum yield. Signoff design rule check (DRC), design for manufacturability (DFM), layout vs schematic (LVS) and metal fill runsets and tech files are available today from GF.
“With its best-in-class performance, power consumption, and integration capability, our differentiated 22FDX platform continues to be the solution of choice for designers and innovators working in 5G mmWave, Edge AI, IoT, and automotive applications,” said Richard Trihy, vice president of design enablement at GLOBALFOUNDRIES. “We were pleased to partner with Synopsys on this qualification, which signifies to designers they can now confidently signoff designs using IC Validator, while maximizing the high-performance and power efficiency benefits of 22FDX.”
IC Validator, a key component of Synopsys’ Fusion Design Platform™, is a comprehensive and highly scalable physical verification solution including DRC, LVS, programmable electrical rule checks (PERC), dummy metal fill, and design-for-manufacturability (DFM) enhancement capabilities. IC Validator is architected for high performance and scalability that maximizes utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies. It uses both multi-threading and distributed processing over multiple machines to provide scalability benefits that extend to more than a thousand CPUs.
“Physical verification closure within schedule is a key challenge for our customers because of the increasing manufacturing complexity,” said Raja Tabet, senior vice president of engineering, Design Group at Synopsys. “Synopsys and GLOBALFOUNDRIES have a deep collaboration that ensures designers have timely access to performance-optimized runsets. The runsets, in parallel with the scalability of IC Validator’s massively parallel architecture, provide designers with a fast and accurate path to physical signoff closure.”
