Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched a powerful, versatile and time- saving FPGA-based NVMe Data Storage solution to aid in the development of High Performance Computing (HPC) applications such as High Frequency Trading and Machine Learning.
The solution includes an Aldec TySOM embedded prototyping board, up to eight high-bandwidth, low- latency FMC-NVMe daughter cards, and a reference design (including source files and binaries) allowing engineers to fast-track their projects.
“NVMe SSDs are very popular in a wide range of high-performance computing applications, as are FPGAs because of their ability to handle parallel processing, their speed and programmability, plus the fact MPSoC FPGAs also feature ARM processor cores,” comments Louie De Luna, Director of Marketing. “Our newest FPGA-based embedded solution is aimed at engineers developing systems that will combine the power and benefits of NVMe and FPGAs.
The latest addition to the company’s extensive range of FPGA mezzanine cards, the FMC-NVMe provides four Non-Volatile Memory express (NVMe) interfaces. These are connected to a Microsemi PM8532 PCIe Switch, which provides a connection-to-carrier-card via the PCIe x8 GEN3 interface using a standard FMC connector. The FMC-NVMe daughter card supports board stacking (up to eight deep – which means up to 32 NVMe SSDs slots are accessible).
To make life easier for HPC application developers, Aldec has prepared a reference design that can be used with either its TySOM-3A-ZU19EG or TySOM-3-ZU7EV embedded development board. Both boards
are based on Xilinx® ZynqTM UltraScale+ MPSoC technology, which incorporates high-performance application processor (APU) with DDR4 system memory controller and hardened configurable PCIe GEN3 blocks in the programmable logic part. These features enable the boards to implement a rich-featured Root Port of PCIe Root Complex solution to meet the underlying physical layer requirements of the NVMe protocol.