APC-SM Sees Digital Twin Opportunities

DAVID LAMMERS, Contributing Writer

Much of the focus surrounding the ~$50B Chips for America program has centered on supporting semiconductor fabrication within the United States. Soon, serious government money will flow to a more software-centric effort: employing digital twins (DTs) in semiconductor manufacturing.

At the recent Advanced Process Control – Smart Manufacturing (APC-SM 2024) conference, held in Toronto, technical presentations focused on using artificial intelligence/machine learning (AI/ML) and digital twins to perform fault detection, virtual metrology, predictive maintenance, and scheduling-dispatch. The APC-SM conference came as the National Institute of Science and Technology (NIST) finalizes how it will proceed with its Chips Manufacturing USA institute focused on digital twins for the semiconductor industry, with $285 million in funding. Three groups have submitted detailed proposals to NIST, which is expected to pick the winning alliance before the end of this year.

A separate, complementary alliance is working with the National Science Foundation (NSF) to establish a Center for  Digital Twins in Manufacturing (CDTM) that, among other goals, would help create SEMI standards. Supporters of the CDTM envision creating software meta layers that would help fab engineers more easily implement solutions using digital twin and AI/ML techniques. The CDTM would be led by the University of Michigan and Arizona State University, with an array of 13 industrial partners taking part.

The various “intelligent manufacturing” initiatives funded by NIST and the NSF are expected to focus on workforce development. The software meta layers that could help train, for example, an engineer with a chemistry degree who knows how an etch process works in some detail but lacks the data science background to apply digital twin, machine learning, and other data analysis techniques.

Three groups in the running

Last summer, a call went out for organizations to submit proposals for the NIST-administered Chips Manufacturing Institute. Participants at the APC-SM conference said three groups are in the running to take the lead of the institute; one led by Stanford University along with two large U.S.-based equipment companies; another group led by Purdue University, and a third alliance led by the University of Pennsylvania.

The goal is to choose the lead alliance and have the Chips Manufacturing Institute for digital twins up and running in early 2025, an aggressive schedule considering the Notice of Funding Opportunity was announced in early June by NIST, an agency of the U.S. Department of Commerce.

Multiple manufacturing challenges were identified during a NIST preparatory roadmap project. Source: APC-SM 2024

To prepare, NIST appropriated $300,000 to several universities – the University of Michigan, the University of Cincinnati, N.C. State, and a private company, Predictronics — to interview dozens of companies and research labs about what they sought from the Chips Manufacturing Institute. The Advanced Manufacturing Technology Roadmap Program is preparing its final report now, intended to help define the roadmap for the future of intelligent semiconductor manufacturing in the United States.

University of Michigan professor James Moyne said “a digital twin is a purpose-driven replica of some aspect of something. That’s the key.” (Photo by Sriram Thiyagarajan)

In early January 2025, the Biden-Harris Administration announced that the U.S. Department of Commerce and the Semiconductor Research Corporation Manufacturing Consortium Corporation (SRC) are entering negotiations for the Department to provide SRC $285 million to establish and operate a Manufacturing USA institute headquartered in Durham, North Carolina. With combined funding totaling $1 billion, this investment will support the launch of the first-of-its-kind CHIPS Manufacturing USA institute. The new institute, known as SMART USA (Semiconductor Manufacturing and Advanced Research with Twins USA) will focus on efforts to develop, validate, and use digital twins to improve domestic semiconductor design, manufacturing, advanced packaging, assembly, and test processes.

Click here to read the full article in Semiconductor Digest.

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