Nearly every new technology breakthrough in the semiconductor industry targets high volume manufacturing and comes with its unique specificities. This results in challenges for engineers to manufacture and test new integrated circuits (ICs) on the wafer.
Die Crack Detection in HVM is Critical for High Reliability Applications
The detection of cracks after the wafer is diced into individual die has become critical in high reliability applications, like the automotive market, where there are substantial safety and liability concerns.
Building Stronger, Better Designs with DTCO CMP Modeling and Simulation
Predicting CMP damage has always been a part of the manufacturing process, but in a Design-technology co-optimization (DTCO) flow, foundries and EDA companies can work together to automate CMP model building and simulation.
Innovative Approaches to Vacuum Enable High-Volume Atomic Layer Processing
Processes such as atomic layer deposition and etch require fast, repetitive, complete exchange of gases in the process chamber. Vacuum equipment manufacturers have responded with solutions that address the challenges presented by these high flow applications.
Process Watch: A Statistical Approach to Improving Chip Reliability
The Process Watch series explores key concepts about process control—defect inspection, metrology and data analytics—for the semiconductor industry. This article is the fifth in a series on process control strategies for automotive semiconductor devices.
Examining Chip Manufacturing Challenges for Advanced Logic Architecture
A look at the critical issues that will have to be addressed to cost-effectively produce the next generation of faster, denser chips.
Process Control Needs Are Increasing Across Semiconductor Fabs
To increase yields and tool uptime, there is a growing need in the front-end of the fab to use wireless sensors.
Bayesian Machine Learning Enables a Virtual Defect Pareto Through Software Simulation
A Failure Mechanism Pareto can be derived through software by applying Bayesian Machine Learning to diagnostic fault simulations.
DVCon U.S. Serves Chip Users Latest Tools and Standards
The Design and Verification Conference and Exhibition (DVCon U.S.) held earlier this year once again brought chip developers together with EDA tool vendors to tackle major issues. By John Blyler, Contributing Editor To practicing chip design and verification engineers, DVCon…
DRAM, NAND and Emerging Memory Technology Trends and Developments in 2019
Innovation in memory technology is constant. In this article, TechInsights’ Jeongdong Choe reviews the latest developments in DRAM, NAND, and emerging technology, and provide insight on the trends in this space.
