Axiomise, a provider of cutting-edge formal verification solutions, today launched footprint, an efficient and fast area analyzer solution designed to transform power, performance and area (PPA) optimization for silicon design.
PPA has become an even bigger challenge than it was previously, a result of larger AI/ML hardware designs. footprint, powered by the new Axiomiser™ platform, discovers redundant gates and registers in complex system on chips (SoCs) that consume power but are never used. The area analyzer solution finds component-level granularity to precisely identify which design components never get used while still consuming power. Synthesis solutions cannot always clean out the redundant area.
“footprint is a key step in realizing our vision of making formal normal,” remarks Dr. Ashish Darbari, Founder and CEO of Axiomise. “This powerful tool provides architects and designers with a quick feedback loop during design bring-up, enabling them to exhaustively analyze silicon waste while optimizing for power and performance.”
Axiomise will showcase footprint at DVCon U.S. 2025 as a Silver Sponsor in Booth #102 from Monday, February 24, through Wednesday, February 26, at the Doubletree by Hilton Hotel in San Jose, Calif. Dr. Darbari and his team will be available to answer questions and discuss the latest advancements in formal verification. To schedule a demo or a meeting, contact [email protected].
