SCOTT BIBAUD, President and Chief Executive Officer, Atomera
Moore’s Law has conditioned the industry to expect a new node to improve power, performance, area and cost (PPAC) by 15-20% every few years. For decades, such improvement in PPAC justified the cost of building a new fabrication plant — leading the industry to use the 15-20% PPAC improvement as a rule of thumb when it comes to justifying a new fab. However, with the slowdown of Moore’s Law, the economics are not so clear cut. The newest manufacturing nodes have become so costly to develop, less frequent (stretching to as long as four years between nodes), and expensive to build ($15-20B), that only the largest or highest volume chips can justify the development and manufacturing costs.
For industries such as automotive, mobile and industrial equipment that use older, or “mature” product nodes where building a new fab is often unfeasible, PPAC improvements must be found elsewhere. Therefore, the old 15-20% economic rule of thumb is just bad math for these enhancements. It’s time for the semiconductor industry to rethink the economics in the post Moore’s Law era.
Enhancing the mature nodes
While improved PPAC in mature nodes can come from building a more advanced fab, that is the exception rather than the rule. Instead, there are other techniques available that provide better improvements at a lower cost than building a new fab.
Incremental PPAC improvements may come through upgrading equipment, using advanced manufacturing techniques in older nodes, or simply through small technology tweaks initiated by the manufacturing process engineers. But even those provide only modest improvements. For more significant PPAC gains, the industry turns to new advanced material technology that improves profitability with minimal capex and development costs.
Time for a new approach
Product managers who are still assuming they need to achieve a 15-20% PPAC improvement to enhance their mature node products are misled by bad math, since the investment needed to enhance an existing node is far smaller than that required to create a new node. Instead, they should be looking at the improved profitability of their product, rather than simply the die shrink enabled by a new technology. Profitability can be improved in many ways, including market share growth or ASP increases due to higher performance, smaller die area /more chips per wafer, and more sales and profit per wafer. Sales gains due to higher performance are notoriously difficult to predict since no one can be sure how the market will react to the enhancement. Instead, engineers and product managers tend to focus on die size reduction as it is directly associated with profitability. However, die size reduction alone is too simplistic to understand the full potential for lower costs. By looking at gross margin, instead of fixating on the traditional 15-20% die shrink target, companies can decide what process redesign makes the most financial sense.
Click here to read the full article in Semiconductor Digest magazine.
