Kneron, the San Diego-based edge AI solutions provider backed by the likes of Alibaba, Sequoia, Horizons Ventures, Qualcomm, and SparkLabs Taipei, today announces its new state of the art AI chip: the Kneron KL720.
Packaging
Research Shows Thin-Film Lithium Niobate Photonic Integrated Circuits are Fundamentally Scalable and Highly Cost-Effective, Ideal for Use in Telecommunications and Quantum Computing
Scientists from HyperLight, a leader in the commercialization of lithium niobate (LN) integrated optical circuits, have teamed with Harvard University researchers to achieve a significant technical milestone for photonic integrated circuits (PICs).
Cadence IC Packaging Reference Flow Certified for the Latest TSMC Advanced Packaging Solutions
Cadence Design Systems, Inc. today announced the certification of the Cadence tools in TSMC reference flows for TSMC’s latest InFO and CoWoS advanced packaging solutions, the Integrated Fan-Out with RDL interconnect (InFO-R) and Chip-on-Wafer-on-Substrate with silicon interposer (CoWoS-S).
Intel Collaborates with Argonne National Laboratory, DOE in Q-NEXT Quantum Computing Research
Intel today announced that it is among the leading U.S. quantum technology companies included in Q-NEXT, one of five new national quantum research centers established by the White House Office of Science and Technology Policy (OSTP) and the U.S. Department of Energy (DOE).
Keysight Survey Reveals True Costs of Time Delays Caused by Test Equipment Misconfiguration, Maintenance and Training Issues
Keysight Technologies, Inc. has released the results of a third-party survey, conducted by Dimensional Research, that shows nearly all companies who design and develop electronic products, experience costly and preventable delays related to test equipment misconfiguration, maintenance or training issues.
Synopsys Collaborates with TSMC to Accelerate 3nm Innovation, Enabling Next-Generation SoC Design
Synopsys, Inc. (Nasdaq: SNPS) today announced that TSMC has certified Synopsys’ digital and custom design platforms for TSMC’s 3-nanometer (nm) process technology. This certification, based on TSMC’s latest design rule manual (DRM) and process design kits (PDKs), is the result of an extensive collaboration with rigorous validation to deliver design solutions for optimized power, performance, and area (PPA), which accelerate the path to next-generation designs.
Marvell and TSMC Collaborate to Deliver Industry’s Most Advanced Data Infrastructure Portfolio on 5nm Technology
With this collaboration, Marvell and TSMC are advancing the essential technology underpinning this infrastructure to provide the storage, bandwidth, speed, and intelligence that tomorrow’s digital economy demands.
SEMI Statement on New U.S. Export Control Regulations
SEMI, the industry association serving the global electronics design and manufacturing supply chain, today released the following statement in response to the new export control rule changes announced by the United States Commerce Department.
High-Function Polyol Additives Improve Performance of Electronics Adhesives
Adhesives used in electronics assemblies must perform without fail to protect delicate components from vibration and heat. They must also be able to secure the components without interfering with the operation of the end product.
Monzukuri Unveils First Commercially-Available IC/Package Co-Design Tool
Monozukuri S.p.A, today unveiled GENIO, the first commercially available IC/Package Co-Design Tool. The company said that it is able to take orders for GENIO now. GENIO is revolutionary fully integrated, design environment-agnostic end-to-end IC and packaging co-design EDA platform for 2D/2.5D/3D system design.
