StratEdge Corporation announced its assembly services for attaching gallium nitride (GaN) and other high-frequency, high-power devices using gold-tin (AuSn) and gold-silicon (AuSi) onto copper-molybdenum-copper (CMC) tabs. StratEdge’s proprietary eutectic die attach method maximizes the power output a chip can achieve, optimizing its performance and providing an efficient way to dissipate heat to avoid overheating and failures during normal operation.
Packaging
Intel Introduces Tremont Microarchitecture
Today at the Linley Fall Processor Conference in Santa Clara, Calif., Intel revealed the first architectural details related to Tremont. Intel’s newest and most advanced low-power x86 CPU architecture, Tremont offers a significant performance boost over prior generations.
ASE Group Significantly Advances Semiconductor Packaging Development With ANSYS Customization Toolkit Solution
ASE Group (ASE) engineers have drastically improved their integrated circuit (IC) semiconductor packaging and development process to create state-of-the-art microchips thanks to ANSYS (NASDAQ: ANSS). Developing an ANSYS Customization Toolkit (ACT) solution, engineers create more accurate models, enhance structural reliability and slash design time to enable customers to receive products faster than ever.
North American Semiconductor Equipment Industry Posts September 2019 Billings
North America-based manufacturers of semiconductor equipment posted $1.95 billion in billings worldwide in September 2019 (three-month average basis), according to the September Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 2.4 percent lower than the final August 2019 level of $2.00 billion, and is 6.0 percent lower than the September 2018 billings level of $2.08 billion. “Monthly billings of North American equipment manufacturers declined for the second consecutive month,” said Ajit Manocha, president and CEO of SEMI.
ESD Alliance Takes SMART Design to SEMICON Europa
The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner, today unveiled SMART Design, the first system-centric series showcasing advances in electronic system design to be held at SEMICON Europa. SEMICON Europa will begin Tuesday, November 12, through Friday, November 15, at Messe München in Munich, Germany. SMART Design is scheduled for Wednesday, November 13, from 2:30 p.m. until 5 p.m. in TechARENA 1, Hall B1.
Samsung Expands its Commitment to Foundry Customers with the First ‘SAFE Forum 2019’
Samsung Electronics Co., Ltd. today held the first Samsung Advanced Foundry Ecosystem (SAFE™) Forum 2019 in the United States. By sharing the latest technology trends and strengthening cooperation within the foundry ecosystem, Samsung showcased its strong dedication to customers. SAFE Forum is designed to provide an opportunity for SAFE partner companies to directly meet with customers to discuss comprehensive design technology infrastructure, including electronic design automation (EDA), intellectual property (IP), cloud, design service, and packaging, which is critical to efficiently developing and manufacturing semiconductor products.
New Transient-Voltage-Suppression Diodes from STMicroelectronics Deliver Higher Protection in Smaller Packages
In addition to the lower profile, ST’s new 1500W SMB Flat package has transient-power capability equivalent to that of conventional devices in SMC packages, in a footprint more than 50% smaller. The 400W and 600W SMA Flat and SMB Flat devices are fully footprint-compatible with alternatives in conventional SMA and SMB packages. Leakage current is five times lower compared with other TVS diodes on the market, minimizing impact on system operation and power consumption.
Paving a Way to Achieve Unexplored Semiconductor Nanostructures
Nanowire is a rod-structure with a diameter typically narrower than several hundred nanometers. Due to its size and structure, it exhibits characteristic properties which are not found in larger bulk materials. The study of III-V semiconductor nanowires has attracted much interest in recent decades due to their potential application in nanoscale quantum, photonic, electronic, and energy conversion, and in biological devices, based on their one-dimensional nature and large surface to volume ratio.
Synopsys Design Platforms Enabled for Samsung Foundry 2.5D-IC Multi-Die Integration
Synopsys, Inc. today announced availability of design solutions to support Samsung Foundry’s 2.5D-IC Multi-Die Integration (MDI™) on its 7-nanometer (nm) LPP (Low Power Plus) with extreme ultraviolet (EUV) lithography technology, known as 7LPP. The Synopsys Fusion Design Platform™ and Custom Design Platform enable quicker design prototyping and analysis to help designers address the time-to-market pressures associated with delivery to accelerating markets, such as 5G, artificial intelligence (AI), and high-performance computing (HPC).
Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology
The use of multiple stacked chips in a single package is becoming a key trend for mobile, IoT and data center designs, which is also extending into the AI and 5G market segments due to the rapid and efficient integration of complete functions that can be implemented via the optimal process node into a system in package (SiP). The Cadence technology provides customers with analysis, implementation and physical verification capabilities within a single canvas and offers unique, early-stage system-level pathfinding and highly-complex design capabilities for 3D signoff. The Cadence flow has been optimized to enable customers to achieve all the benefits the Samsung Foundry MDI packaging technology has to offer in order to deliver new products to market with greater speed and agility.
