Hopefully everyone is familiar with the International Technology Roadmap for Semiconductors (ITRS). It was launched in 1992, when the Semiconductor Industry Association (SIA) coordinated the first efforts of producing what was originally The National Technology Roadmap for Semiconductors (NTRS). This roadmap of requirements and possible solutions was generated three times in 1992, 1994, and 1997. The NTRS provided a 15-year outlook on the major trends of the semiconductor industry. As…
Pete’s Posts
Challenges of 10nm and 7nm CMOS at IEDM
The International Electron Devices Meeting (IEDM) was held in Washington, D.C. this week. I attended a short course on Sunday focused on the Challenges of 10nm and 7nm CMOS Technologies, organized by Aaron Thean of imec. The speakers were Frederic Boeuf of ST Microlelectronics, who gave a general overview of drivers and challenges; Zsolt Tokei of imec, who spoke on interconnect challenges; Andy Wei of GLOBALFOUNDRIES who talked about process…
Countdown to The ConFab 2014
We had our second conference call yesterday with advisory board of The ConFab (a special thanks to Lori Nye of Brewer Science who called in from Japan at 2:00 am her time. Above and Beyond the call of dutry!). The ConFab will be held June 22-25 at The Encore at The Wynn in fabulous Las Vegas, Nevada. It will be the 10th anniversary of the event and I’m working hard…
IEDM’s special focus session highlights diverse challenge
As part of the technical program at the annual IEEE International Electron Devices Meeting (IEDM), scheduled for December 9 – 11, 2013 at the Washington Hilton Hotel, a special focus session has been planned to highlight advanced processing and platforms for semiconductor manufacturing technology, including ‘more-than-Moore’ applications. The technical session, scheduled for Tuesday, December 10 from 9am – 12pm, will feature presentations on many of today’s hot topics: memory, LEDs,…
Progress in Intrachip Optical Interconnects and Silicon Photonics
In a keynote talk at The ConFab earlier this year, Samsung exec Yoon Woo (Y.W.) Lee. predicted that optical interconnects would soon be required. “Exascale computing will require optical interconnection to communicate between the CPU and memory chip,” he said. This appears to be moving closer to reality with last week’s demonstration by Fujitsu and Intel of the world’s first Optical PCIe Express (OPCIe) based server. Intel’s 50Gbps silicon photonics…
SST’s Editorial Calendar for 2014 is Out
The new Solid State Technology Editorial calendar for 2014 – the whole media planner actually – is out and live on our site: http://electroiq.com/advertise-docs/2014mediakit.pdf The editorial mission remains that same: we’re dedicated to covering mainstream semiconductor manufacturing technology, with a strong focus on transistors, interconnects and packaging. We also cover other types of advanced electronics, including MEMs, LEDs, displays, bioelectronics, photonics and power electronics. In 2014, we’ll be looking at…
Should lifetime of EUV optics be a concern?
It’s well known that EUV adoption is running later than hoped, mostly due to inadequate source power (although ASML and Cymer say they are on track to provide workable solutions and imec says it’s on track for the 10nm node). After that, the main challenge could be those associated with EUV mask blanks, which are essentially sophisticated mirrors. The dual challenge there is that they are not only difficult to…
What’s down the road for bulk FinFETs
For the 10nm node and beyond, transistor research efforts are focused on high mobility designs with Ge and III-V channel, reducing VDD supply voltage as well as the subthreshold slope in transistors and optimizing multi-Vt designs. Eventually, lateral finFETs built from silicon nanowires may be required. As previously reported in the post “Status update on logic and memory roadmaps,” the 14nm node (which imec calls the “N” node”) is in…
EUV is late but on the way for 10nm; DSA is promising
EUV lithography is late, but it is on the way and will be ready for insertion into the 10nm node, which is slated to go into production in late 2015/early 2016. Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. These were some of the conclusions…
Intel stands firm on 450mm; challenged by defects at 14nm
Brian Krzanich, chief executive officer of Intel, said Intel is standing firm on 450mm development (despite rumors to the contrary), during a quarterly conference call with financial analysts. He also blamed defects on a slight push-out of next-generation 14nm technology. When asked about 450mm plans, Krzanich said: “We have not changed our timing. We are still targeting the second, latter half of this decade. We continue to see great value…
