After slowing in the past couple years, semiconductor merger and acquisition activity strengthened in the first eight months of 2019 with the combined value of about 20 M&A agreement announcements reaching $28.0 billion for the purchase of chip companies, business units, product lines, intellectual property (IP), and wafer fabs between January and the end of August.
Semiconductors
New Architected Material Shape-Changes to Tune Its Qualities
Architected materials are comprised of micron and nanoscale structures like crossbeams, arches, domes, and spirals, much like the elements of a building’s architecture. Researchers from the California Institute of Technology, the Georgia Institute of Technology, and ETH Zurich have made an architected material that shifts the shapes of these structures. When a slight current is applied, nanoscale beams thicken and bend into arches that increasingly bow as the current is boosted. The material maintains the new shape even when the current is off, and the shape can be changed back by reversing the current. Both are novel characteristics.
North American Semiconductor Equipment Industry Posts September 2019 Billings
North America-based manufacturers of semiconductor equipment posted $1.95 billion in billings worldwide in September 2019 (three-month average basis), according to the September Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 2.4 percent lower than the final August 2019 level of $2.00 billion, and is 6.0 percent lower than the September 2018 billings level of $2.08 billion. “Monthly billings of North American equipment manufacturers declined for the second consecutive month,” said Ajit Manocha, president and CEO of SEMI.
FEFU and FEB RAS Scientists Are Close to Integrating Silicon Electronics and Spintronics
Scientists from Far Eastern Federal University (FEFU) and the Far Eastern Branch of the Russian Academy of Sciences (FEB RAS) developed the nanoheterostructure consisted of a nanocrystal magnetite film (Fe3O4) covering a silicon substrate with an additional layer of silicon oxide (SiO2/Si). Its magnetic and magnetotransport properties may help to design highly efficient hybrid semiconductor devices with new spintronic elements. The related article was published in the Journal of Alloys and Compounds.
ESD Alliance Takes SMART Design to SEMICON Europa
The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner, today unveiled SMART Design, the first system-centric series showcasing advances in electronic system design to be held at SEMICON Europa. SEMICON Europa will begin Tuesday, November 12, through Friday, November 15, at Messe München in Munich, Germany. SMART Design is scheduled for Wednesday, November 13, from 2:30 p.m. until 5 p.m. in TechARENA 1, Hall B1.
MKS Announces Release of Ultra-Fast C-Series Mass Flow Controllers
MKS Instruments, Inc. today announced the release of its next generation C-Series Mass Flow Controllers. The C-Series Mass Flow Controller uses Micro-Electromechanical Systems (MEMS) technology combined with a fast-acting control valve and MKS’ proprietary algorithms resulting in an ultra-fast control time of less than 100 milliseconds. The C-Series product is available in several configurations with multiple I/Os, process connections and flow ranges to address a wide variety of customer applications.
NUS Innovation Paves the Way For Sensor Interfaces That Are 30 Times Smaller
The Green IC research group in the Department of Electrical and Computer Engineering at the National University of Singapore’s (NUS) Faculty of Engineering invented a novel class of Digital-to-Analog (DAC) and Analog-to-Digital Converters (ADC) that can be entirely designed with a fully-automated digital design methodology, thanks to its fully-digital architecture. Compared to traditional analog architectures and methodologies, the design turnaround time for these novel sensor interfaces is reduced from months to hours. The drastic reduction in the design effort is highly beneficial in cost-sensitive silicon systems, such as sensors for the Internet of Things (IoT). The novel data converter architecture also has very low complexity, reducing the silicon area and hence the manufacturing cost by at least 30 times, compared to conventional designs.
US Department of Defense to Invest up to $170M in SkyWater’s Domestic Technology Foundry
SkyWater Technology, the innovator’s trusted partner for a competitive edge, announced the US Department of Defense (DOD) is planning to invest up to $170 million for a multi-phase project to enhance microelectronics capabilities for the DoD and the Strategic Radiation Hardened (Rad-Hard) market. SkyWater will be expanding its Trusted Foundry facility to add clean room area and supporting infrastructure to enable this and other complementary technologies. The initial phase is funded at $80 million and SkyWater will leverage this investment to develop a new 90 nm rad-hard electronics production capability to complement its existing 90 nm rad-tolerant offering. In addition, it will fund SkyWater to add copper (Cu) dual-damascene interconnect technology to the facility which marks a significant advancement for the company’s mixed-signal and interposer offerings. Future phases of the effort include options for more advanced microelectronics capabilities.
Wafer Capacity by Feature Size Shows Rapid Growth at <10nm
Leading-edge processes (<28nm) took over as the largest portion in terms of monthly installed capacity available in 2015. By the end of 2019, <28nm capacity is forecast to represent about 49% of the IC industry’s total capacity, based on information in IC Insights’ Global Wafer Capacity 2019-2023 report.
Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its custom and analog/mixed-signal (AMS) IC design flow has achieved certification for Samsung Foundry’s 5nm Low-Power Early (5LPE) process technology. This certification ensures mutual customers of Cadence and Samsung Foundry have immediate access to a highly automated circuit design, layout, signoff and verification flow needed to design efficiently at 5LPE.
