Guest Contributor: Bryon Moyer, Editor of EE Journal Sensor fusion has been all the rage over the last year. We’ve all watched as numerous companies – both makers of sensors and the “sensor-agnostic” folks – have sported dueling algorithms. Sensor fusion has broadened into “data fusion,” where other non-sensor data like maps can play a part. This drama increasingly unfolds on microcontrollers serving as “sensor hubs.” But there’s something new…
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IEDM’s special focus session highlights diverse challenge
As part of the technical program at the annual IEEE International Electron Devices Meeting (IEDM), scheduled for December 9 – 11, 2013 at the Washington Hilton Hotel, a special focus session has been planned to highlight advanced processing and platforms for semiconductor manufacturing technology, including ‘more-than-Moore’ applications. The technical session, scheduled for Tuesday, December 10 from 9am – 12pm, will feature presentations on many of today’s hot topics: memory, LEDs,…
Progress in Intrachip Optical Interconnects and Silicon Photonics
In a keynote talk at The ConFab earlier this year, Samsung exec Yoon Woo (Y.W.) Lee. predicted that optical interconnects would soon be required. “Exascale computing will require optical interconnection to communicate between the CPU and memory chip,” he said. This appears to be moving closer to reality with last week’s demonstration by Fujitsu and Intel of the world’s first Optical PCIe Express (OPCIe) based server. Intel’s 50Gbps silicon photonics…
GLOBALFOUNDRIES to make Apple chips in New York fab?
I normally don’t have the time to follow local press, but occasionally Google Alerts pops up with something quite interesting. In this case, the Albany Times Union from Albany, New York had an intriguing headline that supports some of the gossip around Apple’s fabrication plans for their A-series processor chips, up to now fabbed by Samsung. At least in the short term, and from a technology point of view, this…
GLOBALFOUNDRIES to make Apple chips in New York fab?
I normally don’t have the time to follow local press, but occasionally Google Alerts pops up with something quite interesting. In this case, the Albany Times Union from Albany, New York had an intriguing headline that supports some of the gossip around Apple’s fabrication plans for their A-series processor chips, up to now fabbed by Samsung. At least in the short term, and from a technology point of view, this…
SST’s Editorial Calendar for 2014 is Out
The new Solid State Technology Editorial calendar for 2014 – the whole media planner actually – is out and live on our site: http://electroiq.com/advertise-docs/2014mediakit.pdf The editorial mission remains that same: we’re dedicated to covering mainstream semiconductor manufacturing technology, with a strong focus on transistors, interconnects and packaging. We also cover other types of advanced electronics, including MEMs, LEDs, displays, bioelectronics, photonics and power electronics. In 2014, we’ll be looking at…
Should lifetime of EUV optics be a concern?
It’s well known that EUV adoption is running later than hoped, mostly due to inadequate source power (although ASML and Cymer say they are on track to provide workable solutions and imec says it’s on track for the 10nm node). After that, the main challenge could be those associated with EUV mask blanks, which are essentially sophisticated mirrors. The dual challenge there is that they are not only difficult to…
Design Enablement and the Emergence of the Near Platform
By Karen Lightman, managing director of MEMS Industry Group I am pleased to bring you this blog by Silex Microsystem’s Peter Himes, vice president marketing & strategic alliances. Peter reflects on MEMS and while other might lament at the conundrum of the uniqueness of all MEMS process (you can hum it to the tune initially coined by Jean Christophe Eloy of “one process, one product”) Peter instead sees opportunity. Through…
What’s down the road for bulk FinFETs
For the 10nm node and beyond, transistor research efforts are focused on high mobility designs with Ge and III-V channel, reducing VDD supply voltage as well as the subthreshold slope in transistors and optimizing multi-Vt designs. Eventually, lateral finFETs built from silicon nanowires may be required. As previously reported in the post “Status update on logic and memory roadmaps,” the 14nm node (which imec calls the “N” node”) is in…
EUV is late but on the way for 10nm; DSA is promising
EUV lithography is late, but it is on the way and will be ready for insertion into the 10nm node, which is slated to go into production in late 2015/early 2016. Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. These were some of the conclusions…
