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Intel Foundries MEMS for Fuel Cell Start-up Nectar

In the last couple of years there have been announcements that Intel will be acting as a foundry for FPGA company Achronix, PLD maker Tabula and programmable network processor provider Netronome, as well as much speculation about making chips for Apple. All these reports refer to using Intel’s leading-edge 22-nm tri-gate process. However, at CES a couple of weeks ago, my eye was caught by a 200-mm wafer on display…

Intel Foundries MEMS for Fuel Cell Start-up Nectar

In the last couple of years there have been announcements that Intel will be acting as a foundry for FPGA company Achronix, PLD maker Tabula and programmable network processor provider Netronome, as well as much speculation about making chips for Apple. All these reports refer to using Intel’s leading-edge 22-nm tri-gate process. However, at CES a couple of weeks ago, my eye was caught by a 200-mm wafer on display…

Questions and answers on FD-SOI

A month or so ago, we implemented (without much fanfare) the ability to comment and rank articles on this site, and more easily use social media tools. I’d like to call your attention to one interesting exchange, and also invite you to start posting comments of your own. In mid-December, we posted an article titled “STMicro: 28nm FD-SOI is ready for manufacturing” which elicited an interesting comment and response. The…

MEMS is happening in Vegas baby, and it’s coming home with you, too

By Karen Lightman, managing director, MEMS Industry Group Everyone knows the famous refrain, "What happens in Vegas, stays in Vegas." But for MEMS, you’ll want what happens in Vegas to come home with you. Why? Because MEMS at CES has gone waaaaay beyond sensing your touch and letting you play Angry Birds. MEMS Industry Group (MIG) is going back for a second year to International CES — because MEMS is…

IBM surprises with 22nm details at IEDM

Monday afternoon at the 2012 IEEE International Electron Devices Meeting, IBM discussed their 22nm SOI high-performance technology [1], aimed at servers and high-end SoC products. To an extent, this is an extension of the 32nm process, using epitaxial SiGe for the PMOS channels and stress, and dual-stress liners for both NMOS and PMOS strain. However, there were a couple of surprises buried in there — at least for me! The…

IBM surprises with 22nm details at IEDM

Monday afternoon at the 2012 IEEE International Electron Devices Meeting, IBM discussed their 22nm SOI high-performance technology [1], aimed at servers and high-end SoC products. To an extent, this is an extension of the 32nm process, using epitaxial SiGe for the PMOS channels and stress, and dual-stress liners for both NMOS and PMOS strain. However, there were a couple of surprises buried in there — at least for me! The…

Intel details 22nm trigate SoC process at IEDM

After launching their 22nm tri-gate high-performance logic product back in the spring, Intel have been promising to show off their SoC derivative, and yesterday was the day at the 2012 IEEE International Electron Devices Meeting. [1] As you can see from Table 1, we now have six transistor options; the high-voltage transistors use a thicker gate dielectric stack (Fig. 1), and the gate pitch and gate lengths have been tuned…

Intel details 22nm trigate SoC process at IEDM

After launching their 22nm tri-gate high-performance logic product back in the spring, Intel have been promising to show off their SoC derivative, and yesterday was the day at the 2012 IEEE International Electron Devices Meeting. [1] As you can see from Table 1, we now have six transistor options; the high-voltage transistors use a thicker gate dielectric stack (Fig. 1), and the gate pitch and gate lengths have been tuned…

Intel details 22nm trigate SoC process at IEDM

After launching their 22nm tri-gate high-performance logic product back in the spring, Intel have been promising to show off their SoC derivative, and yesterday was the day at the 2012 IEEE International Electron Devices Meeting. [1] As you can see from Table 1, we now have six transistor options; the high-voltage transistors use a thicker gate dielectric stack (Fig. 1), and the gate pitch and gate lengths have been tuned…

Present your ideas at The ConFab in 2013

The ConFab is now accepting abstract submissions for our 2013 conference, to be held June 23-26 in Las Vegas. If you’re an executive at a leading semiconductor manufacturer and would like to present at The ConFab and participate in three days of productive meetings and roundtable discussions, we’d like to hear from you! We’re presently recruiting speakers for the following topics: • Economic outlook of the semiconductor and related industries…

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