James Huang, Vice President of R&D, Alchip Technologies sees a chiplet revolution as the cost-effective extender of Moore’s Law.
In a technical address at TSMC’s 2021 Open Innovation Platform, Mr. Huang stressed that chiplet’s and advanced packaging provides competitive cost structure versus monolith SoCs, while maintaining comparable performance and power consumption.
Huang cited two pieces of technology that will be critical chiplet/packaging developments: One is TSMC’s 3DFabric and CoWos® combined technologies. The other is Alchip’s APLink die-to-die I/0.
The APLink die-to-die (D2D) I/0 enables high speed data traffic between multiple chiplets. APLink 1.0 targets TSMC’s 12nm process, while APLink 2.0 targets that foundry’s 7nm process is. APLink 3.0 is currently undergoing test chip results evaltion, having achieved its target line rate. Line rates for APLink 1.0 and 2.0 are 1 gigabit per second and 4 gigabites per second respectively.
Stepping beyond the present, Huang gave attendees a peak of what’s to come. Detailing what he refered to as APLink 4.0, he revealed the 3nm-targeted D2D IP.
APLink 4.0’s interconnect topology will feature a Source-synchronous I/O bus running with standard core voltage. The IP is speced to run at 12Tbps per PHY macro, with speeds of up to 16Gbps per DQ line, but with only 5 nano-seconds of latency. Taken together, this will result in reliable system operations.
The APlink 4.0 IP will support both north/south and east/west orientations and a symmetric PHY alignment that will minimize D2D wire length.
“But what makes this even more aligned with the needs of future technology innovation is a flexible business model that brings the futurere to reality,” Huang pointed out.
When implemented, Alchip’s customer engagement model will offer entry points at the product spec, SoC design and systems bring-up entry points.
