MOZ AHMED, Edge & Embedded Technology Solutions Manager at Mobica,
AI is revolutionising entire industries. By next year, it’s expected the world will generate over 180 zettabytes of data. As a result, a fundamental shift in computing power is needed to cater for the development of these data-hungry innovations.
In response to this need, one solution that’s gaining traction is heterogeneous computing. This enables a single system to have multiple computing sub-systems, such as CPUs, GPUs, DSPs, FPGAs and ASICs. These processors execute core instructions differently, but work in parallel to help increase compute speed and lower the time required to complete a task. The result? A more seamless user experience in instances where vast amounts of data need to be processed and converted – such as AI and machine learning workloads.
A balancing act
For those wishing to push ahead, a heterogeneous system on chip (SoC) is stacked with possibilities. Typically when designing a system, there’s some kind of tradeoff between flexibility, performance and cost. For instance, general purpose computing might provide the most flexibility, but loses ground on performance and cost. And because application-specific computing is designed for a particular use case, it impresses when it comes to performance, but this comes at a price and with less flexibility. In contrast, embedded computing is the least flexible, but typically available for the lowest cost.
How, then, does a heterogeneous SoC solve this problem? First, it breaks the link between performance and flexibility. This means a system can scale up to meet increased demands if required. Secondly, by taking advantage of intelligent features like smart scheduling, it breaks the link between flexibility and cost, so as many processors can be employed for as many tasks as possible. Finally, this increased flexibility and scalability results in a more efficient, cost-effective system, which can competently manage multiple tasks.
Opting for custom chip designs
When considering heterogeneous SoCs, there are real gains to be made from custom chip designs or processing blocks in an SoC. These are tailored to specific application requirements, while providing more control when integrating hardware and software.
Custom chip designs can also deliver greater cost efficiencies. Because the chip is designed for a specific use case, fewer inessential features are implemented, reducing design and fabrication costs. In turn, there are fewer functions consuming power, which minimises energy usage, and auxiliary components can be designed with a lower specification on the printed circuit board. A simpler design also means simpler implementation, making the system easier to manage and troubleshoot, which reduces ongoing maintenance costs. And with fewer functions taking up valuable silicon space, a custom chip not only lowers costs but provides more chips per wafer, improving each wafer’s yield too.
The emergence of custom instructions supported by RISC-V also provides an opportunity to further optimize the use of custom processors.
Click here to read the full article in Semiconductor Digest.
