Over the last few decades, the exponential explosion in computing power has relied on ever shrinking transistor dimensions. The size reduction of the smallest features patterned on silicon wafers has been largely enabled by advances in lithography, a process which uses light, a mask as a design template, and a photosensitive material cast on the wafer to define patterns. Innovations in lithography equipment in the last 40 years have allowed us to print smaller and smaller features by using shorter wavelengths of light and by increasing the numerical aperture (or NA) of the machines’ optics. However, the evolution of these machines alone is insufficient to achieve their ultimate resolution in real world devices.
The semiconductor industry has also relied on innovations in computational techniques, mask, material, and processes, as well as novel patterning schemes. Taken together, these all help improve the yield (or number of usable chips) at the desired dimensions and tolerances for the pattern on a wafer.
The next-generation lithography equipment, High NA EUV (High Numerical-Aperture Extreme Ultraviolet), is here, and will allow the semiconductor industry to find even more ways to scale down the size of the features of transistors. But as with every new lithography technology in years past, there are significant challenges to overcome to accelerate its insertion into production. IBM and its ecosystem partners are working on now to bring this once-in-a-decade technology to bear as quickly as possible.
For the past decade, the semiconductor industry has depended on EUV lithography machines from ASML, which use lasers with a wavelength of 13.5nm to achieve high-resolution patterning down to 13nm (26nm pitch). One of the first EUV machines in the world was installed in the Albany Nanotech Complex, owned and operated by NY CREATES, in 2014. IBM Research is an anchor partner of NY CREATES, where we work alongside researchers from the State University of New York (SUNY), Tokyo Electron (TEL), and many others.
Since then, IBM Research and its partners have built a vibrant ecosystem supporting the development and optimization of EUV lithography that has allowed the production of advanced chips at scale for 7nm, 5nm, and most recently, 2nm technology nodes. One of the clearest examples of how much EUV lithography has evolved is in the patterning of the metal lines that connect transistors, called interconnects. These tend to be some of the smallest dimensions printed on a wafer and as such were identified as the first insertion opportunity for EUV lithography.
In 2015, IBM and its partners demonstrated the first implementation of EUV lithography technology, enabling us to design circuits with 36nm pitch copper lines with self-aligned contacts, half the size of what could be naturally printed with prior lithography technology, ushering in the EUV logic era. This enabled aggressively scaled integrated circuits, laying the foundation for better performance and power saving. Though the EUV machines were capable of printing 26nm pitch features, there were many hurdles limiting manufacturing implementation of this size feature.
The expected challenges of equipment throughput and availability, mask defectivity, and availability of photoresist (resist) materials that could harness EUV wavelengths, were all tackled. Less expected challenges were also discovered. Specifically, stochastic effects related to the limited number of photons used in EUV imaging, combined with the nature of the imaging material itself, surfaced as the major yield detractor for the technology. It became clear to us that advancing this technology further would require more robust test vehicles and methodologies to develop comprehensive patterning solutions. These would need to be evaluated with ultimate performance metrics, such as electrical yield.
Since that first EUV insertion point, and subsequent innovation needs, IBM has continued to push the limits of EUV lithography, leveraging all the capabilities of the Albany NanoTech ecosystem to fuel innovation. With our partner TEL, we have established a fully integrated copper damascene patterning baseline, which we have gradually refined through continuous cycles of co-optimization of virtually all aspects of patterning technology. Building off this robust baseline, we now have been able to demonstrate mature ramp-up electrical yields for transistor interconnects at 28 nm pitch, which were directly patterned with EUV lithography using metal oxide resist materials. We have demonstrated stable yields with a robust process window for unbroken copper lines longer than 1m long, demonstrating the benefit of co-optimizing across multiple process areas like lithography, films, and etch in this partnership.
Along the decade-plus journey of driving EUV yield performance to its resolution limit, we have made significant learning on the photoresist imaging materials themselves. Though organic chemically-amplified resists have been the workhorse of EUV patterning for most of that time, we have seen the best yields at the EUV resolution limit with recent advancements in various types of metal oxide resists, both spin-on and dry-deposited. On this note, we have recently obtained champion yields at 28nm and 26nm pitch copper damascene interconnects with dry-deposited metal oxide resists with our partners from Lam Research, allowing the integrated patterning process in Albany to realize the full potential of EUV technology to date with this best-known process available today.
However, the demands for further scaling have not stopped at the limit of resolution that Low NA EUV can provide. As with previous technologies, the industry has had to leverage patterning schemes that rely on multipatterning EUV to achieve the desired critical dimensions. Multipatterning techniques usually rely on complex patterning stacks and integration schemes that often come with performance and yield issues, as well as restrictions on the design on the wafer — and significantly higher costs and cycle times.
To break through these limitations, ASML developed High NA EUV systems, which increases the numerical aperture in the machine’s optics to improve resolution to a theoretical limit of 16nm pitch features (a 40% improvement in resolution from prior EUV technology). High NA EUV allows process engineers simplify their patterning schemes, reducing manufacturing complexity and potentially cost reductions. High NA EUV also offers process simplification and cycle time reduction, as well as a path towards designing high-performance logic devices below the 2nm node. This has the potential to extend the Nanosheet era and enable future vertically-stacked transistors beyond the 1nm node.
There are, however, key challenges to overcome to accelerate the insertion of High NA EUV, some of which are familiar technology challenges shared with EUV lithography. These include stochastic effects that lead to reduced yield, throughput challenges that increase cost of ownership, and imaging aberrations caused by the topology of the masks. There are also unique challenges to the adoption of this new lithography equipment related to the unprecedented 67% jump from the current 0.33 to 0.55 in numerical aperture, such as field size reduction, and a much higher sensitivity to any undulation in the silicon wafer surface. As with the first generation of EUV adoption, solving these challenges will require co-optimizing solutions across the patterning process space.
The road to accelerating the insertion of this technology into high volume manufacturing has just started. Earlier this year, ASML and imec opened the High NA lab in Veldhoven, Netherlands with the first research and development tool for High NA EUV. Researchers from IBM are leveraging this partnership to start working on how we will deploy this technology in our future nodes.
Using this new lithography technology from ASML, and leveraging the experience and established integrated patterning baseline in the NY CREATES ecosystem, IBM has already achieved early demonstration of metallization of lines down to 21nm pitch (see figure above) that enables the continuation of copper damascene interconnects integration that IBM pioneered almost 30 years ago, unlocking the needs of semiconductor designs below the 2nm node and simplifying future Nanosheet node technology. What’s more, the single-print 24, 23, and 21 nm pitch interconnects have demonstrable and consistent electrical functionality. This demonstrates that IBM’s development platform can continue to leverage further process co-optimization to enable mature yields in these smallest of wires, as was achieved for the insertion of 36nm pitch single-print EUV.
As IBM Research continues to drive the roadmap for logic scaling in support of the diversified computing platform of the future, the open model of collaboration within the NY CREATES ecosystem will continue to be a key enabler for advanced patterning solutions for the next decade.
