Today at the Linley Fall Processor Conference in Santa Clara, Calif., Intel revealed the first architectural details related to Tremont. Intel’s newest and most advanced low-power x86 CPU architecture, Tremont offers a significant performance boost over prior generations.
“Tremont is Intel’s most advanced low-power x86 architecture to date. We focused on a range of modern, complex workloads, while considering networking, client, browser and battery so that we could raise performance efficiently across the board. It is a world-class CPU architecture designed for enhanced processing power in compact, low-power packages.”
–Stephen Robinson, Intel Tremont Chief Architect
Tremont next-generation low-power x86 microarchitecture delivers significant IPC (instructions per cycle) gains gen-over-gen compared with Intel’s prior low-power x86 architectures. Designed for enhanced processing power in compact, low-power packages, Tremont-based processors will enable a new generation of innovative form factors for client devices, creative applications for the internet of things (IoT), efficient data center products and more.
When combined with other technologies across Intel’s broader IP portfolio, this architecture will enable a new generation of products. Using Intel’s 3D packaging technology Foveros, Tremont is integrated within a wider set of silicon IPs in Lakefield, which will power breakthrough innovative devices like the recently announced dual-screen Microsoft Surface Neo.
Performant architectures are the foundation of chips that capture and process data. Low-power solutions are essential to enabling new use cases driven by smaller form factors.
Intel Tremont includes several advancements in ISA (instruction set architecture), microarchitecture, security and power management. It delivers significant IPC gains gen-over-gen as compared with Intel’s prior low-power x86 architectures, making it a first-class offering for powering a new generation of Intel products across client, IoT and data center offerings. Tremont’s unique 6-wide (2×3-wide clustered) out-of-order decoder in the front end allows for a more efficient feed to the wider back end, which is fundamental for performance.
