More is Better: Epitaxial Multilayer MoS2 Wafers with Promises in High-Performance Transistors

Two-dimensional (2D) semiconductors, such as MoS₂, enable the unprecedented possibilities to solve the bottleneck of transistor scaling and to build novel logic circuits with faster speed, lower power consumption, flexibility and transparency, benefiting from their ultra-thin thickness, dangling-bond-free flat surface and excellent gate controllability. In 2015, International Technology Roadmap for Semiconductors (ITRS) clearly pointed out that 2D semiconductors are key materials for next-generation high-performance devices. In 2021, Intel listed 2D MoS₂-based transistor technology as one of the three breakthrough technologies for the next decade.

Tremendous efforts have been devoted to exploring the scaled-up potentials of monolayer MoS₂, including both wafter-scale synthesis of high-quality materials and large-area devices. In terms of a further improvement of the electronic quality of the large-scale monolayer MoS₂, structural imperfections should be eliminated as much as possible; however, there is not much space left for monolayer MoS₂ after ten years of synthesis optimizations in this field. Another key direction is to switch to multilayer MoS₂, e.g., bilayers and trilayers, since they have intrinsically higher electronic quality than monolayers and thus are conducive to higher-performance devices and logic circuit. However, due to the fundamental limitation of thermodynamics, it is still a great challenge to realize wafer-scale multilayer MoS₂ with high-quality and large-scale uniformity.

In a study published in National Science Review, a research team from China has now overcome the fundamental limitations of thermodynamics by exploiting the proximity effect of substrate and achieved, for the first time, the growth of high-quality multilayer MoS₂ 4-inch wafers via the layer-by-layer epitaxy process. The epitaxy leads to well-defined stacking orders between adjacent epitaxial layers and offers a delicate control of layer numbers up to 6.

‘To achieve the layer-by-layer epitaxy of multilayer MoS₂, we independently design an oxygen-assisted 4-inch multi-source CVD system. The breakthrough of controllable epitaxy of high-quality multilayer MoS₂ wafers would lay a solid material foundation for large-scale high-performance 2D electronic devices, and is expected to play a paramount role in sub-10 nm ultra-short channel devices, flexible displays and smart wearable devices,’ says Dr. Qinqin Wang, the first author of the work.

Compared to monolayers, thicker-layer MoS₂ field-effect transistors show significant improvements in device performances. For long-channel devices, the average field-effect mobility at room temperature can increase from ~80 cm²·V^-1·s^-1 for monolayers to ~110/145 cm²·V^-1·s^-1 for bilayer/trilayer devices, improved by 37.5%/81.3%. For trilayer MoS₂ field-effect transistors, the highest room temperature mobility can reach up to 234.7 cm²·V^-1·s^-1, setting a new mobility record for devices based on 2D transition-metal sulfide semiconductors. For devices with channel-length of 100 nm, the current density (V_ds=1 V) is increased from 0.4 mA·μm^-1 for monolayer to 0.64/0.81 mA·μm^-1 for bilayer/trilayer, showing an enhancement factor of 60%/102.5%. Remarkably, for 40 nm short-channel devices, a record-high on-current densities of 1.70/1.22/0.94 mA/μm at V_ds=2/1/0.65 V, as well as a high on/off ratio exceeding 10⁷, are achieved in trilayer MoS₂ field-effect transistors.

‘Considering that, in well-developed thin-film transistors (TFTs), field-effect mobility is 10-40 cm²·V^-1·s^-1 for indium–gallium–zinc-oxide TFTs and 50-100 cm²·V^-1·s^-1 for low-temperature polycrystalline silicon TFTs, the competitive average field-effect mobility, e.g., larger than 100 cm²·V^-1·s^-1, achieved in this work strongly uncover a great potential of these multilayer MoS₂films for high-performance TFT applications,’ says Dr. Jian Tang, one of the lead authors of the work.

‘The on-current density of trilayer MoS₂ devices with a channel length of 40 nm can reach a record-high value of 1.70 mA/μm at V_ds=2 V, outperforming the previous state-of-the-art MoS₂ transistors. Such high on-current density also exceeds the target of high-performance logic transistors from the International Roadmap for Devices and Systems (IRDS) 2028, and hence moves a step closer to practical applications of 2D MoS₂ in electronics and logic circuits at sub-5 nm nodes,’ adds Professor Guangyu Zhang, who leads the group behind the study.