Rambus Inc. today unveiled industry-first, complete memory interface chipsets for Gen5 DDR5 RDIMMs and next-generation DDR5 Multiplexed Rank Dual Inline Memory Modules (MRDIMMs). These innovative new products for RDIMMs and MRDIMMs will seamlessly extend DDR5 performance with unparalleled bandwidth and memory capacity for compute-intensive data center and AI workloads.
The new Rambus chips include:
- The Gen5 Registering Clock Driver (RCD), enabling RDIMMs operating at 8000 megatransfers per second (MT/s).
- The Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB), enabling upcoming MRDIMMs running at speeds up to 12,800 MT/s by doubling the bandwidth of the DIMM beyond the native DRAM device speed.
- The second-generation server Power Management IC (PMIC5030) designed for both DDR5 RDIMM 8000 and MRDIMM 12800, providing ultra-high current at low voltage to support higher speeds and more DRAM and logic chips per module.
“The voracious memory demands of AI and HPC require the relentless pursuit of higher performance through continued innovation and technology leadership,” said Sean Fan, chief operating officer at Rambus. “With our 30-plus years of renowned high-speed signal integrity and memory system expertise, the Rambus Gen5 RCD, and next-generation MRCD, MDB, and PMIC will be critical enabling chips in future-generation servers leveraging DDR5 RDIMM 8000 and MRDIMM 12800.”
Enabling flexible and scalable end-user server configuration, the DDR5 RDIMM 8000 and industry-standard MRDIMM 12800 utilize a common architecture with compatibility across server platforms. The DDR5 RDIMM 8000 chipset includes the Gen5 RCD, PMIC5030, Serial Presence Detect (SPD) Hub and Temperature Sensor (TS) chips. The DDR5 MRDIMM 12800 chipset includes the MRCD and MDB, as well as the same PMIC5030, SPD Hub and TS chips utilized in the RDIMM 8000.
The DDR5 MRDIMM 12800 employs a novel and efficient module design that boosts data transfer rates and system performance by multiplexing two ranks of DRAM, effectively interleaving the two data streams. This allows the host memory bus to run at twice the data rate of the native DRAM devices, thus increasing bandwidth while using the same physical connections of DDR5 RDIMMs. This requires an MRCD that can address the two ranks of DRAMs on alternate clock cycles, as well as MDBs to direct the data stream to and from the correct DRAM devices. Each DDR5 MRDIMM 12800 requires one MRCD and ten MDB chips to multiplex the memory channel. The MRCD and MDB will also support a Tall MRDIMM form factor with four ranks of DDR5 DRAMs for double the capacity of a dual-rank RDIMM in a cost-effective manner.
The Gen5 RCD, MRCD, MDB and PMIC5030 are part of the growing Rambus portfolio of industry-leading memory interface and power management solutions including Gen1 to Gen4 RCD, Client Clock Driver (CKD), Server PMIC, SPD Hub, and TS chips.