Samsung Electronics today unveiled plans for continuous process technology migration to 3- and 2-nanometer (nm) based on the company’s Gate-All-Around (GAA) transistor structure at its 5th annual Samsung Foundry Forum (SFF) 2021.
With a theme of Adding One More Dimension, the multi-day virtual event is expected to draw over 2,000 global customers and partners. At this year’s event, Samsung will share its vision to bolster its leadership in the rapidly evolving foundry market by taking each respective part of foundry business to the next level: process technology, manufacturing operations, and foundry services.
“We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continuing technological innovation by application,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. “Amid further digitalization prompted by the COVID-19 pandemic, our customers and partners will discover the limitless potential of silicon implementation for delivering the right technology at the right time.”
GAA is ready for customers’ adoption – 3nm MP in 2022, 2nm in 2025
With its enhanced power, performance and flexible design capability, Samsung’s unique GAA technology, Multi-Bridge-Channel FET (MBCFETTM), is essential for continuing process migration. Samsung’s first 3nm GAA process node utilizing MBCFET will allow up to 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. In addition to power, performance, and area (PPA) improvements, as its process maturity has increased, 3nm’s logic yield is approaching a similar level to the 4nm process, which is currently in mass production.
Samsung is scheduled to start producing its customers’ first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023. Newly added to Samsung’s technology roadmap, the 2nm process node with MBCFET is in the early stages of development with mass production in 2025.
FinFET for CIS, DDI, MCU – 17nm specialty process technology debuts
Samsung Foundry is continuously improving its FinFET process technology to support specialty products with cost-effective and application-specific competitiveness. A good example of this is the company’s 17nm FinFET process node. In addition to the intrinsic benefits afforded by FinFET, the process node has excellent performance and power efficiency leveraging a 3D transistor architecture. Consequently, Samsung’s 17nm FinFET provides up to 43 percent decrease in area, 39 percent higher performance, or a 49 percent increase in power efficiency compared to the 28nm process.
Additionally, Samsung is advancing its 14nm process in order to support 3.3V high voltage or flash-type embedded MRAM (eMRAM) which enables increased write speed and density. It will be a great option for applications such as micro controller units (MCUs), IoT and wearables. Samsung’s 8nm radio frequency (RF) platform is expected to expand the company’s leadership in the 5G semiconductor market from sub-6GHz to mmWave applications.
Looking ahead, in cooperation with its ecosystem partners, Samsung Foundry’s SAFE Forum will be held virtually in November 2021.
Be cautious Dr. Choi:
Based on pure mathematical modelling I can postulate a theory which will predict a uncontrolled Quantum Tunnelling information shift paradox. If the chip crosses a critical number of lepton transfusion moment, number of lepton controlled active site (transistor) and number of silicon atom and volume then we predict a Quantum Tunnelling information shift paradox among all the semiconductor chips in the world at a time. That means once it crosses the set limit all the semiconductor chips made of the same configuration will experience this cataclysm at the same time. I can prove mathematically this can happen when it crosses 3nm to 2nm and having the mathematically calculated Lepton Controlled Active Site (transistor), silicon/silicon oxides/boron/phosphorus, etc. volume and Lepton shifting volume.
The information shift paradox will have a definite relationship between number of chips, number of systems, number of data processing speed transfer of lepton, minimum number of chips operating together, silicon lepton active site density.