DAVE LAMMERS, contributing editor
Logic scaling is proceeding at a surprisingly robust pace, alongside equally important efforts to put multiple chiplets in a package, speakers said at the IEEE 2022 Symposium on VLSI Technology and Circuits, held in Honolulu June 13-17.
Christopher Patrick, a senior vice president at Qualcomm, kicked off the conference with a keynote that outlined the choices chip architects now face as the industry expands from primarily a system-on-chip (SoC) design methodology to a System on Multichip (SoMC) approach.
Patrick heads up Qualcomm’s handset IC division, where volumes are high and costs are of paramount importance. The slowing “tailwind” of Moore’s Law, which allowed Qualcomm to regularly add functions to its consumer-use SoC solutions, has led the industry to consider System on Multichip designs. But technical challenges to the SoMC approach are varied, including test and thermal issues. Multichip designs require die-to-die interfaces which support multiple voltage domains, and Patrick said “we need better modeling and floor planning, and tools for co-designing the package and system. We have to be able to partition the design and decide if we want 2D, 2.5D, or 3D integration, and how to decide on the right combination of technology nodes.”
Asked if Qualcomm is moving to SoMC-based products which combine Qualcomm-designed die with off-the-shelf chiplets, Patrick said the multi-die approach offers “modularity benefits” that would support using older nodes for some functions. But there are supply chain challenges: “the access to older nodes is limited; the capacity is not readily available.”
Besides the daunting thermal and test challenges for SoMC designs, the packaging infrastructure must evolve quickly. “There are many technical challenges to the multi-die approach. It is unclear how we handle the Known Good Die issues, and yield loss during assembly. But the history of the semiconductor industry is that we take the complex and make it seem trivial, and we do it at a rapid pace.”
Shrink roadmap slowing down
In a video keynote speech, Martin van den Brink, CTO at ASML, said ASML is striving to improve the productivity of its EUV tools, improving the availability to 90 percent uptime and 3,000 wafers per day of throughput.
“Our ambition is to eventually get to 400 to 500 wafers per hour,” an increase from the 2023 target of 200 to 300 wph on the NXE 3800 tool. “We are very confident we can drive up productivity, partly by increasing the source output to 300 Watts. The metal oxide resists will support better resolution. We are really in an era of high-volume manufacturing with EUV,” van den Brink said.
Click here to read the full article in Semiconductor Digest magazine.
