Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with TSMC to develop a broad portfolio of DesignWare®interface IP, logic libraries, embedded memories, and one-time programmable (OTP) non-volatile memory (NVM) IP on TSMC’s 5-nanometer (nm) FinFET Plus (N5P) Process. The DesignWare IP solutions for TSMC’s N5 process will enable designers to achieve aggressive performance, density, and power targets for their mobile and cloud computing designs. This collaboration reinforces the longstanding relationship between the two companies to provide designers with the high-quality IP needed to lower risk, differentiate their system-on-chips (SoCs), and accelerate their time-to-market.
“For nearly two decades, TSMC has been collaborating closely with Synopsys to help our mutual customers accelerate their time to volume by providing a broad range of proven DesignWare IP on TSMC’s most advanced processes,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “We’re pleased with the results of our collaboration in enabling designers to achieve an acceleration on their advanced mobile and cloud computing SoCs while gaining the full performance and power benefits of TSMC’s newest and industry-leading process technology.”
“As the leading provider of interface IP, Synopsys continues to make significant investments in developing high-quality IP on the latest process technologies, so designers can gain the performance, power, and area advantages that help differentiate their SoCs,” said John Koeter, vice president of marketing for IP at Synopsys. “Our collaboration with TSMC on the development of Synopsys’ DesignWare IP for the N5P process will enable designers to achieve their aggressive design goals and accelerate their project schedules in today’s fast-moving markets.”
