Synopsys, Inc. (Nasdaq: SNPS) today announced that Synopsys, Arm, and Samsung have actively collaborated on solutions to enable early adoption of the next-generation Arm®-based processor. Design-ready solutions are based on the artificial intelligence (AI)-enhanced, cloud-ready Fusion Design Platform™ from Synopsys, along with Arm Artisan®Physical IP and POP™ IP for Samsung Foundry’s advanced 5LPE process. These solutions will accelerate development of the next wave of semiconductor system-on-chips (SoCs), including designs for high-performance computing (HPC), automotive, 5G, and AI market segments. The collaboration will help customers optimize power, performance, and area (PPA), and achieve faster time-to-market while providing full-flow quality-of-results (QoR) and time-to-results (TTR).
“To address the pace of innovation in our industry, close collaboration between partners to enable mutual customers is essential,” said Paul Williamson, senior vice president and general manager, Client Line of Business, Arm. “The work we’re doing with Samsung Foundry and Synopsys on this advanced node enables further optimization to power and performance for next-generation Arm-based devices.”
“Synopsys’ Fusion Design Platform and QuickStart Implementation Kits provide a design-ready solution for next-generation Arm-based processors,” said Jaehong Park, executive vice president of Foundry Design Platform Development at Samsung Electronics. “This is a great example of how Samsung 5LPE technology can be utilized to give designers a competitive advantage in their high-performance CPU designs. Through our close partnership with Arm and Synopsys, customers will now be able to extract maximum value out of our 5-nanometer processes for design applications targeted at high-performance and low-power markets.”
Synopsys’ Fusion Design Platform has been leveraged for optimized implementation of the new Arm core. The Fusion Design Platform incorporates many Synopsys industry-leading products, including:
- 7nm and below implementation in Fusion Compiler™ design, Design Compiler® graphical synthesis, and IC Compiler™ II place-and-route system
- Higher performance with automatic density control and timing-driven placement
- Lower power with full-flow concurrent clock and datapath (CCD) optimization
- Signoff closure with PrimeTime® PBA-based ECO with power recovery and exhaustive PBA along with StarRC™simultaneous multi-corner extraction
- Early, accelerated design optimization for power integrity and reliability with the RedHawk™ Analysis Fusion signoff-driven flow within IC Compiler II
“Using the latest processors offers early customers the ability to leverage new and innovative technologies for their next-generation products, and to do so, customers need a trusted overall solution to ensure quality-of-results and time-to-market,” said Sassine Ghazi, general manager of the Design Group at Synopsys. “This close collaboration among industry leaders paves the way for better and easier implementation, so designers are able to meet aggressive delivery schedules and achieve their performance, power, and area targets.”
