While chipmakers are moving ahead with technology generations, maintaining the same timeline for scaling transistors in the front-end-of-line (FEOL), contacts and interconnects in the middle- (MOL) and back-end-of-line (BEOL) has become challenging.
While chipmakers are moving ahead with technology generations, maintaining the same timeline for scaling transistors in the front-end-of-line (FEOL), contacts and interconnects in the middle- (MOL) and back-end-of-line (BEOL) has become challenging.
As discussed in my last Ed’s Threads, lithography has become patterning as evidenced by first use of Self-Aligned Quadruple Patterning (SAQP) in High Volume Manufacturing (HVM) of memory chips. Meanwhile, industry R&D hub imec has been investigating use of SAQP…
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