On-chip metal interconnects limit IC speed in many advanced design today, and with signal delay proportional to the product of the resistance (R) of wires and the capacitance (C) of dielectric insulation, wires with R lower than that of copper…
Bottoms-up ELD of Cobalt Plugs
As reported in more detail at Solid State Technology, during the IEEE IITC now happening in Grenoble, imec and Lam showed a new Electroless Deposition (ELD) cobalt (Co) process that is claimed to provide void-free bottoms-up pre-filling of vias and…
Moore’s Law is Dead – (Part 3) Where?
…we reach the atomic limits of device scaling. At ~4nm pitch we run out of room “at the bottom,” after patterning costs explode at 45nm pitch. Lead bongo player of physics Richard Feynman famously said, “There’s plenty of room at…
