Now in its 12th year, the MRAM Global Innovation Forum is the industry’s premier platform that brings together leading magnetics experts, researchers, and industry professionals to share the latest advancements in Magnetoresistive Random Access Memory (MRAM) technology. The annual one-day event will be held the day after the IEEE International Electron Devices Meeting (IEDM) on December 12, 2024 from 8:45am to 6pm at the Hilton San Francisco Union Square hotel’s Imperial Ballroom A/B.
MRAM technology, a type of non-volatile memory, is known for its high speed, endurance, scalability, low power consumption and radiation hardness. Unlike conventional memory technologies, data in MRAM devices is stored by magnetic storage elements instead of electric charge. MRAM technology has gained momentum as a solution for embedded memory applications, in areas such as automotive microcontrollers, sensors, aerospace, data centers, wearable devices, and more recently in edge AI devices.
The 2024 MRAM technical program consists of 10 invited presentations from leading global MRAM experts, and an evening panel.
“Since the very first MRAM Global Innovation Forum took place in 2013, MRAM technology has advanced from an initial development stage to where it is now being used in a growing number of applications, ranging from wearables to automotive microcontroller units,” said Kévin Garello, MRAM Forum co-chair and senior research development scientist at SPINTEC. “Major foundries and memory developers are now disclosing exciting MRAM scaling roadmaps for cache and DRAM-like use cases, which will be discussed in this year’s forum”
“The MRAM market is expected to grow by double digits over the next few years,” said Daniel Worledge, MRAM Forum co-chair and senior manager, MRAM at IBM. “Making that growth possible are the contributions of the world’s MRAM experts who gather each year at the MRAM Forum to advance the state-of-the-art in this increasingly vital technology.”
Here are program details of the 2024 MRAM Global Innovation Forum:
Technical Program Presentations (Invited)
The technical program at the MRAM Forum consist of 10 invited talks by leading industry experts, presented consecutively in three technology areas:
Embedded Applications
• High Performance Embedded STT-MRAM for Automotive Applications, Yi Ching Ong, TSMC
STT-RAM is particularly well suited for automotive applications, with superior retention and endurance, making it ideal for next-gen software-defined vehicles using Over-The-Air features. This talk presents a fully-functional high yield N16 MRAM macro with high write throughput and robust endurance, designed to support automotive-grade MCUs.
- MRAM: Status, Improvements, and Opportunities for a Fully Emerged Memory, Steven Soss, GlobalFoundries
Since its inception in 2019 at the 22nm nodes, MRAM has been widely adopted by advanced foundries and IDMs for its excellent scalability, superior reliability, and fast read/write times. Opportunities remain for improvements in process cost reduction and enhancing magnetic immunity, as well as Compute-In-Memory applications.
- World’s Most Energy Efficient eMRAM Technology & Beyond, Tae Young Lee, Samsung
eMRAM has demonstrated its applicability in automotive MCUs and sensors, with high speed, high endurance, energy efficiency, and reliable NVM performance. Through further refinements in magnetic tunnel junction processes, enhancements in MTJ switching efficiency can achieve best-in-class write energy with unlimited endurance.
- MRAM Memory Compilers to Accelerate & Enhance the Experience of Building MRAM Blocks for SOCs, Jamil Kawa, Synopsys
MRAM blocks in automotive SOCs have quickly proliferated, with stringent reliability requirements, configuration flexibility, comprehensive testing, tight power budgets, reduced cost and time to market as the dominant requirements. Design of efficient MRAM compilers frees systems designers to focus on SOC and system objectives, while evaluating alternative MRAMs in a short period.
Standalone Applications & Markets
• Reliable Memory Operation with Low Read Disturb Rate in the World’s Smallest 1Selector-1MTJ Cell for 64Gb Cross-Point MRAM, Hisanori Aikawa, KIOXIA
While STT-RAM based on 1-MTJ/1-transistor cells have entered the market in standalone and embedded forms, truly high density MRAM still lacks select transistor driveability against MTJ writing current. This talk presents breakthroughs for high density cross-point MRAM, such as As-doped SiO2 selectors employed to ensure enough write-current in the on-state with low leakage current in the off-state.
- STT-MRAM for PERSYST Solutions in Industrial/Automotive Markets, Sanjeev Agarwal, Everspin
MRAM technology has matured, leading to its acceptance for volume production in data centers, industrial products, wearable devices, and aerospace applications. The latest STT-MRAM products are aimed at industrial applications requiring low latency, high speed, low bit-error rate, and high reliability; as well as enhancements that will enable qualification to automotive standard AEC-Q100 Grade 1. - MRAM Market Dynamics & Technology Trends, Simone Bertolazzi, Yolé Group
Emerging nonvolatile memory (NVM) technologies such as MRAM, PCM, and ReRAM are gaining momentum in embedded applications for code/data storage in microcontrollers, low power IoTs, wearables, and edge-AI devices. This talk provides an overview of the emerging memory competitive landscape, detailing market dynamics of embedded MRAM across various market segments.
Exploratory Topics
• Ultra-Fast & Low Power STT-Switching of Ferrimagnetic Heusler Alloys for MRAM, Panos Filippou, IBM
STT-MRAM MTJ devices with conventional CoFeB magnetic electrodes suffer at high speeds due to high overdrive currents required to switch the free layer. Ferrimagnetism enables Mn3Ge Heusler alloy MTJs that can be switched efficiently at high speed, enabling reduced switching currents and denser STT-RAM.
- Path Toward Process Integration of Ultimately Scaled SOT-MRAM Arrays, Farrukh Yasin, imec
SOT-MRAM has gained interest for its sub-ns switching speed and high endurance, required for high speed NVM applications such as SRAM last level cache replacement. In-plane SOT-MRAM arrays have inherent MTJ shape anisotropy, leading to large SOT size. Reducing SOT device footprint is critical to scale bit-cell size for high density NVM, and perpendicular SOT-RAM is an ideal candidate. - Design & Integration of Novel MTJ Devices in a Mixed Signal Discovery Platform, Christopher Bennett, Sandia National Labs
Array-scale memory demos with complex compute-in-memory are critical to validate memory process fabrication yields and verification of key circuit building blocks. Large scale spintronic array demos have validated small MTJ arrays. This talk describes a 32×32 mixed-signal array with increased flexibility and functionality, including digital bit-cell masking and a novel 2.5D heterogeneously integrated approach.
Panel Session
Following the technical presentations, there will be a panel discussion on the theme, “Opportunities & Risks of MRAM in the Era of High-Performance Computing & AI.” This year’s panel will be moderated by Jean Anne Incorvia of the University of Texas at Austin. Panelists include:
- Steven Soss, GlobalFoundries
- Sanjeev Aggarwal, Everspin Technologies
- Christopher Bennett, Sandia National Laboratories
- John Wuu, AMD
Registration
Attendance at the 2024 MRAM Global Innovation Forum is complimentary but limited to 250 participants. Registration is open until December 1, 2024. Lunch is included with registration.