Synopsys, Inc. (Nasdaq: SNPS) today announced it has received four 2020 OIP Partner of the Year awards for IP and EDA solutions from TSMC demonstrating excellence in next-generation system-on-chip (SoC) and 3DIC design enablement. These awards recognize Synopsys for high-quality interface IP, the joint development of 3-nanometer (nm) design infrastructure, 3DIC design productivity and a highly scalable timing sign-off solution in the cloud.
For more than 20 years, Synopsys and TSMC have collaborated to accelerate development and innovation, including the adoption of FinFET technology for optimum power, performance, and area (PPA) for TSMC’s N3 process. 2020 is the tenth consecutive year Synopsys has received IP and electronic design automation (EDA) accolades from TSMC.
“We’re pleased to congratulate Synopsys as the winner of multiple 2020 OIP Partner of the Year awards for IP and EDA solutions in recognition of our collaboration to enable important innovations in the field of semiconductor design,” said Suk Lee, senior director of Design Infrastructure Management Division at TSMC. “TSMC looks forward to our continued partnership to address our customers’ needs with certified design solutions using TSMC’s latest technologies and extend the development of PPA-optimized design platforms for automotive, mobile, HPC, AI and 5G applications.”
The companies’ long-standing collaboration has over the past year yielded impressive achievements for the benefit of mutual customers, including:
- TSMC certification of new, innovative features in Synopsys’ digital and custom implementation platforms extended to 3nm enablement for early customer engagements
- Synopsys’ 3DIC Compiler with its tightly integrated, full-chip array of chip package, co-design and analysis capabilities accelerates advanced 2.5D/3DIC packaging design productivity and faster time to an optimal solution
- Highly scalable Synopsys’ PrimeTime® static timing analysis and StarRC™ signoff extraction technology for use in the cloud providing significant throughput gains and considerable cost savings for design closure
- Synopsys has delivered a broad portfolio of silicon-proven DesignWare® IP on TSMC’s N7 and N5 processes for advanced SoCs targeting data-intensive applications including HPC and AI
“For over two decades, Synopsys and TSMC have been collaborating to accelerate silicon innovation and help customers achieve their time-to-market goals,” said Charles Matar, senior vice president of System Solutions and Ecosystem Enablement for the Design Group at Synopsys. “Our close and deep engineering engagement with TSMC has led to innovative solutions like 3DIC design enablement, 3nm design implementations, and DesignWare interface IP, as well as ongoing efforts to optimize the TSMC Open Innovation Platform® Virtual Design Environment (OIP VDE) cloud solution. These innovative solutions have enabled mutual customers to take advantage of Synopsys’ proven, design platforms and IP portfolio using TSMC’s latest process technologies.”
