VSORA, provider of high-performance silicon intellectual property (IP) solutions for artificial intelligence (AI), digital communications and advanced driver-assistance systems (ADAS) applications, today unveiled a family of PetaFLOPS computational companion chips to accelerate Level 3 (L3) through Level 5 (L5) autonomous vehicle designs.
The first full silicon solution from VSORA, Tyr™ uses a proprietary and scalable architecture to achieve unparalleled performance built on the VSORA AD1028 architecture awarded “Best Processor IP in 2020” by The Linley Group.
Delivering between 258-trillion and 1,032-trillion operations per second and consuming as little as 10 Watts, Tyr allows users to implement autonomous driving functions previously not commercially viable.
Tyr, a family of three different chips called Tyr1, Tyr2 and Tyr3, offers a fully programmable architecture that tightly couples digital signal processing (DSP) cores with machine learning (ML) accelerators necessary to design L3 through L5 autonomous driving vehicles. The Tyr companion chip is algorithm and host processor agnostic and can be integrated into new or existing environments without the need to redesign the entire system.
“We are proud to be the first to offer the ability to rapidly move to full autonomy utilizing what designers have already invested in,” remarks Khaled Maalej, CEO and founder of VSORA. “The Tyr family is the first in a series of companion chips from VSORA to provide global vehicle manufacturers early commercial availability of L3 to L5 functionality.”
The modular architecture of the Tyr family is well suited to meet the challenges of autonomous driving. With a computational power of 1,032 TeraFLOPS, the Tyr3 processes an eight-million cell particle filter using 16-million particles in less than 5 milliseconds (msec). A full-high-definition (FHD) image with Yolo-v3 takes less than 1.6 msec leading to a throughput of 625 images per second.
The Tyr family is implemented using VSORA’s proprietary low-power architecture to achieve more than 80% usage efficiency approximating the theoretical maximum processing power, eliminating the need for expensive multi-chip or hardware accelerator solutions or special cooling solutions.