The IEEE Electronic Components and Technology Conference (ECTC), the world’s premier technical conference and product exhibition for the semiconductor packaging industry, has announced the winners of its prestigious Best and Outstanding Paper Awards for 2024. The awards are given annually to recognize the most noteworthy ECTC presentations which describe significant advances in the design and development of microsystems packaging and manufacturing.
“We are proud to announce that after in-depth evaluations of nearly 400 technical presentations given at ECTC 2024 in May 2024 in Denver, CO, the following papers have been recognized as the Best and Outstanding contributions in their respective categories,” said Michael Mayer, ECTC 2025 Vice General Chair and Professor in the department of Mechanical & Mechatronics Engineering at the University of Waterloo.
“These awards are given based on the potential impact of the work on design and manufacturing of semiconductor packaging, the likely industry impact, and the overall contribution to the body of knowledge in a specific area,” he said.
The Best and Outstanding Session Papers from ECTC 2024:
- 74th ECTC 2024 Best Session Paper – “Advanced Thermocompression Bonding on High Density Fan-Out Embedded Bridge Technology for HPC/AI/ML Applications.” Co-authored by Wiwy Wudjud, ShuYu Lin, Yungshun Chang, Jean Yen, Reno Liao, LeoHS Cheng, Yihsien Wu, Simon YL Huang, Jui Tzu Chen, ChengYu Lee and JoeyCl Huang; all with Advanced Semiconductor Engineering, Inc. FOCoS-Bridge (fan-out-chip-on-substrate-embedded bridge) technology is an innovative approach to connecting chiplets of various types in high-density arrangements for high-performance computing, artificial intelligence, and machine learning (HPC/AI/ML) applications. One issue is that these disparate chiplets have different coefficients of thermal expansion, leading to potential warpage. This paper describes the use of thermocompression bonding to resolve warpage issues in a large chip module incorporating 10 chiplets and 10 silicon bridge dies, which combined, account for >3X silicon reticle size.
- 74th ECTC 2024 Outstanding Session Paper – “3-Layer Fine Pitch Cu-Cu Hybrid Bonding Demonstrator with High-Density TSV for Advanced CMOS Image Sensor Applications.” Co-authored by Stéphane Nicolas, Jerzy-Javier Suarez-Berru, Nicolas Bresson, Carole Socquet-Clerc, Myriam Assous, Stéphan Borel, Rémi Vélard, Jérôme Dechamp, Renan Bouis, Antonio Roman, Karine Abadie and Damien Hebras, from CEA-Leti/Univ. Grenoble Alpes. The paper describes the next level of integration for advanced CMOS image sensors: a three-layer test vehicle employing fine-pitch copper-copper hybrid bonding technology and high-density through-silicon vias (TSVs).
Interactive Presentations from ECTC 2024
“Interactive presentations are strongly emphasized at ECTC, because they facilitate extensive one-on-one engagement between presenters and attendees, for content that requires more detailed explanation than is feasible with traditional oral presentations,” Mayer said.
- 74th ECTC 2024 Best Interactive Presentation Paper – “A Novel Plasma Etching Technology of RIE-Lag Free TSV and Dicing Processes for 3D Chiplets Interconnect.” Co-authored by Taichi Suzuki, Kenta Doi and Toshiyuki Nakamura; all with ULVAC, Inc. The paper describes the development and application of a dual-frequency inductively coupled plasma (ICP) etching system for fabrication of 3D-ICs, designed to address the increasing need for efficient CPUs and HBM (high-bandwidth memory) in data centers.
- 74th ECTC 2024 Outstanding Interactive Presentation Paper – “Optimization of Core Material Properties for Large Flip-chip Ball Grid Array Substrate to Manage Both Warpage and Board Level Reliability.” Co-authored by Hirokazu Noma, Masaki Takahashi, Nene Hatakeyama, Yuichi Yanaka, Akito Fukui, Keita Johno and Hitoshi Onozeki; all with Resonac Corp. When a large silicon chip or interposer is mounted onto a large package substrate using flip-chip technology, a critical concern is the reliability not just of the flip-chip joint, but also of the ball grid array (BGA) joint which connects the package to the board. This paper studies the use of four different package substrate materials for controlling package warpage, and their impacts on BGA performance.
Award-Winning Student Papers from ECTC 2024:
- 74th ECTC 2024 Intel Best Student Paper Award (USD $2,500) – “In Situ Analysis of Copper Microstructures in Electromigration Using SEM-EBSD Techniques.” Co-authored by Yaqian Zhang, Yixin Yan, Sten Vollebregt and Guoqi Zhang; all from Delft University of Technology. The paper looks at the behavior of materials which are under stress in highly miniaturized devices, particularly with respect to the phenomenon of electromigration. The paper explores the relationship between copper’s microstructure and electromigration, by combining in situ scanning electron microscopy (SEM) with electron backscatter diffraction (EBSD) to enable real-time observation and analysis of electromigration-induced changes in the microstructure of copper.
- 74th ECTC 2024 Intel Outstanding Student Paper Award (USD $1,500) – “Performance Evaluation of UCIe-based Die-to-Die Interface on Low-Cost 2D Packaging Technology.” Co-authored by Srujan Penta, Ting Zheng, Eric Tremble, Aatreya Chakravarti, Anthony Sigler, Zhonghao Zhang, Carl Benes, Muhannad S. Bakir and Wolfgang Sauter, from Georgia Institute of Technology/Marvell Technology. As chiplet-based designs grow in popularity, die-to-die interconnects have become an increased area of focus with the goal of maximizing system performance. This paper describes the design of a parallel die-to-die interface in a standard 2D package to optimize costs while providing both power and “beachfront” efficiency (i.e., how much data can be sent from the edge of a die). The interface is designed in compliance with the emerging UCIe industry standard for die-to-die interfaces.
- 74th ECTC 2024 Texas Instruments Outstanding Student Interactive Presentation Award (USD $1,500) – “Deep Reinforcement Learning-Based Power Distribution Network Design Optimization for Multi-Chiplet System.” Co-authored by Weiyang Miao, Zhen Xie, Chuan Seng Tan and Mihai D. Rotaru, from Nanyang Technological University/Institute of Microelectronics Agency for Science, Technology and Research (A*STAR), Singapore. The paper describes a deep reinforcement learning (RL)-based AI framework for the design of a package-level power distribution network (PDN) for a multi-chiplet system with 28 power domains. The proposed AI model can generate a viable PDN design much faster quickly than traditional methods, and with lower overall self-impedance.
“Thank you to our award sponsors Intel Corporation and Texas Instruments” said Mayer. “We look forward to the next IEEE ECTC conference – our 75th anniversary – which will take place May 27-30, 2025 at the Gaylord Texan Resort & Convention Center in Dallas, TX.”
