TSMC today unveiled its next cutting-edge logic process technology, A14, at the Company’s North America Technology Symposium. Representing a significant advancement from TSMC’s industry-leading N2 process, A14 is designed to drive AI transformation forward by delivering faster computing and greater power efficiency. It is also expected to enhance smartphones by improving their on-board AI capabilities, making them even smarter. Planned to enter production in 2028, the current A14 development is progressing smoothly with yield performance ahead of schedule.
Compared with the N2 process, which is about to enter volume production later this year, A14 will offer up to 15% speed improvement at the same power, or up to 30% power reduction at the same speed, along with more than 20% increase in logic density. Leveraging the Company’s experience in design-technology co-optimization for nanosheet transistor, TSMC is also evolving its TSMC NanoFlex™ standard cell architecture to NanoFlex™ Pro, enabling greater performance, power efficiency and design flexibility.
“Our customers constantly look to the future, and TSMC’s technology leadership and manufacturing excellence provides them with a dependable roadmap for their innovations,” said TSMC Chairman and CEO Dr. C.C. Wei. “TSMC’s cutting-edge logic technologies like A14 are part of a comprehensive suite of solutions that connect the physical and digital worlds to unleash our customers’ innovation for advancing the AI future.”
In addition to A14, TSMC also debuted new logic, specialty, advanced packaging and 3D chip stacking technologies, each contributing to broad technology platforms in High Performance Computing (HPC), Smartphone, Automotive, and Internet of Things (IoT). These offerings are designed to equip customers with a comprehensive suite of interconnected technologies to drive their product innovations. They include:
High Performance Computing
TSMC continues to advance its Chip on Wafer on Substrate (CoWoS®) technology to address AI’s insatiable need for more logic and high-bandwidth memory (HBM). The company plans to bring 9.5 reticle size CoWoS to volume production in 2027, enabling integration of 12 HBM stacks or more in a package together with TSMC’s leading-edge logic technology. After showcasing its revolutionary System-on-Wafer (TSMC-SoW™) technology in 2024, TSMC followed up with SoW-X, a CoWoS-based offering to create a wafer-sized system with computing power 40X the current CoWoS solution. Volume production is scheduled for 2027.
TSMC offers a host of solutions to compliment the sheer computing power and efficiency of its logic technologies. These include silicon photonics integration with TSMC’s Compact Universal Photonic Engine (COUPE™), N12 and N3 logic base die for HBM4, and a new Integrated Voltage Regulator (IVR) for AI with 5X vertical power density delivery compared with a separate power management chip on the circuit board.
Smartphone
TSMC is supporting AI on edge devices and its need for high-speed, low-latency wireless connectivity to move massive data with N4C RF, the latest generation of TSMC’s radio frequency technology. N4C RF delivers 30% power and area reduction versus N6RF+, making it ideal for packing more digital content into RF system-on-chip designs to meet the requirements of emerging standards such as WiFi8 and AI-rich True Wireless Stereo. It is scheduled to enter risk production in first quarter of 2026.
Automotive
Advanced Driver Assistance Systems (ADAS) and Autonomous Vehicles (AV) pose stringent demands for computing power with no compromise on automotive-grade quality and reliability. TSMC is meeting customers’ needs with the most advanced N3A process going through the final stage of AEC-Q100 Grade-1 qualification, and continuous defect improvement to meet Automotive defective parts per million (DPPM) requirements. N3A is entering production for automotive applications, joining a full suite of technologies for future software-defined vehicles.
Internet of Things
As everyday electronics and appliances adopt AI functionality, IoT applications are taking on greater computational tasks while remaining on a slim budget for battery power. With TSMC’s previously announced ultra-low power N6e process now in production, the company is targeting N4e to continue pushing the envelope of power efficiency for future edge AIs.
TSMC’s North America Technology Symposium in Santa Clara, California, is the Company’s flagship customer event of the year, with more than 2,500 people registered to attend. At the symposium, TSMC not only updates customers on its latest technology developments, it also provides start-up customers with an “Innovation Zone” to showcase their unique products, as well as opportunities to pitch to potential investors. The North America symposium also kicks off a series of Technology Symposiums around the world in the coming months.
