The IEEE Electronic Components and Technology Conference (ECTC) is the world’s premier conference and product exhibition for bringing together the best in chip packaging, components, and microelectronic systems in an environment of cooperation and technical exchange. To be held May 27-30, 2025 at the Gaylord Texan Resort & Convention Center, Dallas in Grapevine, TX near Dallas, ECTC will host more than 2,000 attendees from industry, academia and government. Last year ECTC saw record attendance, a record number of paper submissions and presentations, record international participation, and a sold-out product exhibition hall.
With chips in the news so much recently, the ECTC program can serve as a leading indicator of where the industry is going, because the breakthroughs needed to build future electronic products are revealed in the program. As you know, ways to combine multiple chips into one package are the focus of intense industry efforts, in order to achieve desired performance while avoiding the difficulty/cost of traditional semiconductor scaling according to Moore’s Law. The range of topics to be covered at ECTC 2025 encompasses hybrid bonding; heterogeneous integration (combining different kinds of chips into one package); integration of photonic (light-based) devices into electronic systems; 2.5D/3D/3.5D integration technologies; device/system/wafer-level packaging; and the many reliability, assembly and related technologies needed to drive things forward.
Here are some of the technical highlights. (A previous news release with details of the conference program is pasted below our names, and a “tip sheet” with highlighted papers and selected images can be found at the 2025 ECTC Tipsheet Press Kit.)
- Keynote talk (Wednesday, May 28): Achieving Efficient Zettascale Compute in the AI Era, by Samuel Naffziger, Sr. Vice President & Corporate Fellow at AMD. The demand for high-performance computing, and for the energy to power it, is increasing faster than ever before. Meeting the challenge of delivering this processing power in the AI era requires holistic innovation from the device to the datacenter. This talk will cover these trends and the key technologies needed to power compute growth at a scale we wouldn’t have conceived of just a few short years ago.
- Liquids and chips don’t mix. . .or do they? Hybrid bonding is an advanced chip packaging technology that connects chips via direct copper-to-copper bonds instead of solder joints. It enables high-density 3D connections between chips and wafers, allowing them to be stacked on top of one another in the same package. But as chips get denser the number of required interconnections grows and their sizes decrease, making precise chip-to-chip alignment extremely difficult. At ECTC, Intel researchers will describe the use of fluidic self-alignment, which uses a liquid’s capillary action to align a chip to a bottom wafer. First, liquid-confinement features are fabricated around the bonding areas of the chip and the wafer. Then, a droplet is dispensed into the center of the bonding areas on the wafer. The top dies are transferred onto the droplets, which then spread out to the confines of the patterned area on the bottom surface. Capillary forces from the liquid’s high surface tension precisely align the dies to the lithographic patterns on the bottom wafer, and the liquid is subsequently evaporated. (Paper #22.1)
- Smart image sensors: Edge computing using image sensors is expected to become increasingly important in the future, as data at a network’s “edge” is fed into AI chips to process image data for face and object recognition. With that in mind, Sony researchers will describe a novel process that makes it possible to integrate an AI chip containing a built-in deep neural network (DNN), into the bottom wafer of a conventional two-wafer stacked CMOS image sensor. (Paper 14.4)
- Machine Learning for Better Thermal Management: As electronic systems become more complex and critical to many aspects of life, ensuring their reliability is a growing concern. The heat generated by the operation of these systems is a key reliability issue, and so thermal management concerns cut across many advanced semiconductor technologies. While analytical approaches to estimate thermal resistance in chip wiring have been developed, they are inadequate. At ECTC, IBM researchers will describe how they trained a machine learning (ML) model to rapidly predict the thermal resistance of the wiring in a test chip, at a mean absolute percentage error of less than 15%. That is a remarkable accuracy improvement versus the traditional analytical model used for comparison, which showed 300%. The machine learning approach opens the possibility of more accurate predictions of hotspots in advanced packaging architectures. (Interactive Presentation session #37)
- Startup/Student Innovation Challenge Competition: On Wednesday, May 28, there will be a special session featuring a competition in which both students and start-up companies will pitch their innovative ideas to a jury panel, followed by audience Q&A, jury deliberation, and then awards and a networking event.
